C programming Symbols
Mathematic Symbols
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SuperH 1
SuperH 2
SuperH DSP
SuperH 2E
SuperH 2A without FPU
SuperH 2A with FPU
SuperH 3
SuperH 3E (3 with FPU)
SuperH 3-DSP
SH1
DSP
SH2
SH2E
SH2A
SH3
SH3E
SH4
SH4A
Data Transfer Instructions
mov Rm,Rn
Rm
0110 nnnn mmmm 0011 MT MT 1 1 1 1 1 1 1 1 1 0 0 1 0 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOV (int m, int n)
{
R[n] = R[m];
PC += 2;
}
Example
mov r0,r1 ! Before execution: r0 = 0xFFFFFFFF, r1 = 0x00000000
! After execution: r1 = 0xFFFFFFFF
mov #imm,Rn
imm
1110 nnnn iiiiiiii EX MT 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Mov e Constant ValueStores immediate data, sign-extended to longword, in general register Rn.
Operation
void MOVI (int i, int n)
{
if ((i & 0x80) == 0)
R[n] = (0x000000FF & i);
else
R[n] = (0xFFFFFF00 | i);
PC += 2;
}
Example
1000 mov #0x80,r1 ! r1 = 0xFFFFFF80
1002 mov.w IMM,r2 ! r2 = 0xFFFF9ABC, IMM means @(0x08,PC)
1004 add #-1,r0
1006 tst r0,r0 ! ← PC location used for address calculation for the MOV.W instruction
1008 movt r13
100A bra NEXT ! Delayed branch instruction
100C mov.l @(4,PC),r3 ! r3 = 0x12345678
100E IMM: .data.w 0x9ABC
1010 .data.w 0x1234
1012 NEXT: jmp @r3 ! Branch destination of the BRA instruction
1014 cmp/eq #0,r0 ! ← PC location used for address calculation for the MOV.L instruction
.align 4
1018 .data.l 0x12345678
movi20 #imm20,Rn
imm
0000 nnnn iiii 0000 iiiiiiiiiiiiiiii 1 1
Mov e I mmediate 20 bits of dataStores immediate data that has been sign-extended to longword in general
register Rn.
Operation
void MOVI20 (int i, int n)
{
if (i & 0x00080000) == 0)
R[n] = (0x000FFFFF & (long)i);
else
R[n] = (0xFFF00000 | (long)i);
PC += 4;
}
movi20s #imm20,Rn
imm
0000 nnnn iiii 0001 iiiiiiiiiiiiiiii 1 1
Mov e I mmediate 20 bits of data and S hift Left 8 bitsShifts immediate data 8 bits to the left and performs sign extension to
longword, then stores the resulting data in general register Rn. Using an OR or
ADD instruction as the next instruction enables a 28-bit absolute address to be
generated.
Operation
void MOVI20S (int i, int n)
{
if (i & 0x00080000) == 0)
R[n] = (0x000FFFFF & (long)i);
else
R[n] = (0xFFF00000 | (long)i);
R[n] <<= 8;
PC += 4;
}
mova @(disp,PC),R0
(disp
11000111 dddddddd EX LS 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Mov e Effective A ddressStores the effective address of the source operand into general
register R0. The 8-bit displacement is zero-extended and quadrupled.
Consequently, the relative interval from the operand is PC + 1020 bytes. The PC
is the address four bytes after this instruction, but the lowest two bits of the
PC are fixed at 00.
Note
SH1*, SH2*, SH3*:PC must point to an address specified by (the starting address of the branch
destination) + 2.
Operation
void MOVA (int d)
{
unsigned int disp;
disp = (unsigned int)(0x000000FF & d);
R[0] = (PC & 0xFFFFFFFC) + 4 + (disp << 2);
PC += 2;
}
Example
.org 0x1006
1006 mova STR,r0 ! Address of STR → r0
1008 mov.b @r0,r1 ! r1 = “X” ← PC location after correcting the lowest two bits
100A add r4,r5 ! ← Original PC location for address calculation for the MOVA instruction
.align 4
100C STR: .sdata “XYZP12”
2002 bra TARGET ! Delayed branch instruction
2004 mova @(0,PC),r0 ! Address of TARGET + 2 → r0
2006 nop
Possible Exceptions
Slot illegal instruction
mov.w @(disp,PC),Rn
(disp
1001 nnnn dddddddd LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e Constant ValueStores immediate data, sign-extended to longword, in general register Rn.
The data is stored from memory address (PC + 4 + displacement × 2).
The 8-bit displacement is multiplied by two after zero-extension, and so the
relative distance from the table is in the range up to PC + 4 + 510 bytes. The
PC value is the address of this instruction.
Note
If the following instruction is a branch instruction, it is identified as a slot
illegal instruction.
Operation
void MOVWI (int d, int n)
{
unsigned int disp = (0x000000FF & d);
R[n] = Read_16 (PC + 4 + (disp << 1));
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Slot illegal instruction exception
Data TLB miss exception
Data TLB protection violation exception
mov.l @(disp,PC),Rn
(disp
1101 nnnn dddddddd LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e Constant ValueStores immediate data, sign-extended to longword, in general register Rn.
The data is stored from memory address (PC + 4 + displacement × 4).
The 8-bit displacement is multiplied by four after zero-extension, and so the
relative distance from the operand is in the range up to PC + 4 + 1020 bytes.
The PC value is the address of this instruction. A value with the lower 2 bits
adjusted to 00 is used in address calculation.
Note
If the following instruction is a branch instruction, it is identified as a slot
illegal instruction.
Operation
void MOVLI (int d, int n)
{
unsigned int disp = (0x000000FF & d);
R[n] = Read_32 ((PC & 0xFFFFFFFC) + 4 + (disp << 2));
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Slot illegal instruction exception
Data TLB miss exception
Data TLB protection violation exception
mov.b @Rm,Rn
(Rm)
0110 nnnn mmmm 0000 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e DataTransfers the source operand to the destination.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Note
MOV.B @R0,R1 ;Before execution: @R0 = H'80, R1 = H'00000000
;After execution: R1 = H'FFFFFF80
Operation
void MOVBL (int m, int n)
{
R[n] = Read_8 (R[m]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else
R[n] |= 0xFFFFFF00;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.w @Rm,Rn
(Rm)
0110 nnnn mmmm 0001 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e DataTransfers the source operand to the destination.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVWL (int m, int n)
{
R[n] = Read_16 (R[m]);
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.l @Rm,Rn
(Rm)
0110 nnnn mmmm 0010 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVLL (int m, int n)
{
R[n] = Read_32 (R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.b Rm,@Rn
Rm
0010 nnnn mmmm 0000 LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVBS (int m, int n)
{
Write_8 (R[n], R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.w Rm,@Rn
Rm
0010 nnnn mmmm 0001 LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVWS (int m, int n)
{
Write_16 (R[n], R[m]);
PC += 2;
}
Example
mov.w r0,@r1 ! Before execution: r0 = 0xFFFF7F80
! After execution: @r1 = 0x7F80
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.l Rm,@Rn
Rm
0010 nnnn mmmm 0010 LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVLS (int m, int n)
{
Write_32 (R[n], R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.b @Rm+,Rn
(Rm)
0110 nnnn mmmm 0100 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 1/2 1
Mov e DataTransfers the source operand to the destination.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVBP (int m, int n)
{
R[n] = Read_8 (R[m]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else
R[n] |= 0xFFFFFF00;
if (n != m)
R[m] += 1;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.w @Rm+,Rn
(Rm)
0110 nnnn mmmm 0101 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 1/2 1
Mov e DataTransfers the source operand to the destination.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVWP (int m, int n)
{
R[n] = Read_16 (R[m]);
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
if (n != m)
R[m] += 2;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.l @Rm+,Rn
(Rm)
0110 nnnn mmmm 0110 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 1/2 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVLP (int m, int n)
{
R[n] = Read_32 (R[m]);
if (n != m)
R[m] += 4;
PC += 2;
}
Example
mov.l @r0+,r1 ! Before execution: r0 = 0x12345670
! After execution: r0 = 0x12345674, r1 = @0x12345670
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.b Rm,@-Rn
Rn
0010 nnnn mmmm 0100 LS LS 1 1 1 1 1 1 1 1 1 1 1 1 1/1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVBM (int m, int n)
{
Write_8 (R[n] - 1, R[m]);
R[n] -= 1;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.w Rm,@-Rn
Rn
0010 nnnn mmmm 0101 LS LS 1 1 1 1 1 1 1 1 1 1 1 1 1/1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVWM (int m, int n)
{
Write_16 (R[n] - 2, R[m]);
R[n] -= 2;
PC += 2;
}
Example
mov.w r0,@-r1 ! Before execution: r0 = 0xAAAAAAAA, r1 = 0xFFFF7F80
! After execution: r1 = 0xFFFF7F7E, @r1 = 0xAAAA
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.l Rm,@-Rn
Rn
0010 nnnn mmmm 0110 LS LS 1 1 1 1 1 1 1 1 1 1 1 1 1/1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVLM (int m, int n)
{
Write_32 (R[n] - 4, R[m]);
R[n] -= 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.b @-Rm,R0
Rm
0100 mmmm 11001011 1 2
Mov e Reverse StackTransfers the source operand to the destination.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVRSBM (int m)
{
R[m] -= 1;
R[0] = Read_16 (R[m]);
if ((R[0] & 0x80) == 0)
R[0] &= 0x000000FF;
else
R[0] |= 0xFFFFFF00;
PC+=2;
}
Possible Exceptions
Data address error
mov.w @-Rm,R0
Rm
0100 mmmm 11011011 1 2
Mov e Reverse StackTransfers the source operand to the destination.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVRSWM (int m)
{
R[m]-= 2;
R[0] = Read_16 (R[m]);
if ((R[0] & 0x8000) == 0)
R[0] &= 0x0000FFFF;
else
R[0] |= 0xFFFF0000;
PC += 2;
}
Possible Exceptions
Data address error
mov.l @-Rm,R0
Rm
0100 mmmm 11101011 1 2
Mov e Reverse StackTransfers the source operand to the destination.
Operation
void MOVRSLM (int m)
{
R[m] -= 4;
R[0] = Read_32 (R[m]);
PC += 2;
}
Possible Exceptions
Data address error
mov.b R0,@Rn+
R0
0100 nnnn 10001011 1 1
Mov e Reverse StackTransfers the source operand to the destination.
Operation
void MOVRSBP (int n)
{
Write_8 (R[n], R[0]);
R[n] += 1;
PC += 2;
}
Possible Exceptions
Data address error
mov.w R0,@Rn+
R0
0100 nnnn 10011011 1 1
Mov e Reverse StackTransfers the source operand to the destination.
Operation
void MOVRSWP (int n)
{
Write_16 (R[n], R[0]);
R[n] += 2;
PC += 2;
}
Possible Exceptions
Data address error
mov.l R0,@Rn+
R0
0100 nnnn 10101011 1 1
Mov e Reverse StackTransfers the source operand to the destination.
Operation
void MOVRSLP (int n)
{
Write_32 (R[n], R[0]);
R[n] += 4;
PC += 2;
}
Possible Exceptions
Data address error
mov.b @(disp,Rm),R0
(disp
10000100 mmmm dddd LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e Structure DataTransfers the source operand to the destination.
The 4-bit displacement is only zero-extended, so a range up to +15 bytes
can be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can
be used instead.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVBL4 (int m, int d)
{
long disp = (0x0000000F & (long)d);
R[0] = Read_8 (R[m] + disp);
if ((R[0] & 0x80) == 0)
R[0] &= 0x000000FF;
else
R[0] |= 0xFFFFFF00;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.b @(disp12,Rm),Rn
(disp
0011 nnnn mmmm 00010100 dddddddddddd 1 2
Mov e Structure DataTransfers the source operand to the destination. This
instruction is ideal for data access in a structure or the stack.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVBL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_8 (R[m] + disp);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else
R[n] |= 0xFFFFFF00;
PC += 4;
}
Possible Exceptions
Data address error
movu.b @(disp12,Rm),Rn
(disp
0011 nnnn mmmm 00011000 dddddddddddd 1 2
Mov e Structure Data as U nsignedTransfers a source operand to a destination, performing unsigned data transfer.
This instruction is ideal for data access in a structure or the stack.
The loaded data is zero-extended to 32 bit before being stored in the
destination register.
Operation
void MOVBUL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_8 (R[m] + disp);
R[n] &= 0x000000FF;
PC += 4;
}
mov.w @(disp,Rm),R0
(disp
10000101 mmmm dddd LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e Structure DataTransfers the source operand to the destination.
The 4-bit displacement is multiplied by two after zero-extension, enabling a
range up to +30 bytes to be specified. If a memory operand cannot be reached,
the @(R0,Rn) mode can be used instead.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVWL4 (int m, int d)
{
long disp = (0x0000000F & (long)d);
R[0] = Read_16 (R[m] + (disp << 1));
if ((R[0] & 0x8000) == 0)
R[0] &= 0x0000FFFF;
else
R[0] |= 0xFFFF0000;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.w @(disp12,Rm),Rn
(disp
0011 nnnn mmmm 00010101 dddddddddddd 1 2
Mov e Structure DataTransfers the source operand to the destination. This
instruction is ideal for data access in a structure or the stack.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVWL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_16 (R[m] + (disp << 1));
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 4;
}
Possible Exceptions
Data address error
movu.w @(disp12,Rm),Rn
(disp
0011 nnnn mmmm 00011001 dddddddddddd 1 2
Mov e Structure Data as U nsignedTransfers a source operand to a destination, performing unsigned data transfer.
This instruction is ideal for data access in a structure or the stack.
The loaded data is zero-extended to 32 bit before being stored in the
destination register.
Operation
void MOVWUL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_16 (R[m] + (disp << 1));
R[n] &= 0x0000FFFF;
PC += 4;
}
mov.l @(disp,Rm),Rn
(disp
0101 nnnn mmmm dddd LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e Structure DataTransfers the source operand to the destination.
The 4-bit displacement is multiplied by four after zero-extension, enabling a
range up to +60 bytes to be specified. If a memory operand cannot be reached,
the @(R0,Rn) mode can be used instead.
Operation
void MOVLL4 (int m, int d, int n)
{
long disp = (0x0000000F & (long)d);
R[n] = Read_32 (R[m] + (disp << 2));
PC += 2;
}
Example
mov.l @(2,r0),r1 ! Before execution: @(r0 + 8) = 0x12345670
! After execution: r1 = 0x12345670
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.l @(disp12,Rm),Rn
(disp
0011 nnnn mmmm 00010110 dddddddddddd 1 2
Mov e Structure DataTransfers the source operand to the destination. This
instruction is ideal for data access in a structure or the stack.
Operation
void MOVLL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_32 (R[m] + (disp << 2));
PC += 4;
}
Possible Exceptions
Data address error
mov.b R0,@(disp,Rn)
R0
10000000 nnnn dddd LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e Structure DataTransfers the source operand to the destination.
The 4-bit displacement is only zero-extended, so a range up to +15 bytes
can be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can
be used instead.
Operation
void MOVBS4 (int d, int n)
{
long disp = (0x0000000F & (long)d);
Write_8 (R[n] + disp, R[0]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.b Rm,@(disp12,Rn)
Rm
0011 nnnn mmmm 00010000 dddddddddddd 1 0
Mov e Structure DataTransfers the source operand to the destination. This
instruction is ideal for data access in a structure or the stack.
Operation
void MOVBS12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
Write_8 (R[n] + disp, R[m]);
PC += 4;
}
Possible Exceptions
Data address error
mov.w R0,@(disp,Rn)
R0
10000001 nnnn dddd LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e Structure DataTransfers the source operand to the destination.
The 4-bit displacement is multiplied by two after zero-extension, enabling a
range up to +30 bytes to be specified. If a memory operand cannot be reached,
the @(R0,Rn) mode can be used instead.
Operation
void MOVWS4 (int d, int n)
{
long disp = (0x0000000F & (long)d);
Write_16 (R[n] + (disp << 1), R[0]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.w Rm,@(disp12,Rn)
Rm
0011 nnnn mmmm 00010001 dddddddddddd 1 0
Mov e Structure DataTransfers the source operand to the destination. This
instruction is ideal for data access in a structure or the stack.
Operation
void MOVWS12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
Write_16 (R[n] + (disp << 1), R[m]);
PC += 4;
}
Possible Exceptions
Data address error
mov.l Rm,@(disp,Rn)
Rm
0001 nnnn mmmm dddd LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e Structure DataTransfers the source operand to the destination.
The 4-bit displacement is multiplied by four after zero-extension, enabling a
range up to +60 bytes to be specified. If a memory operand cannot be reached,
the @(R0,Rn) mode can be used instead.
Operation
void MOVLS4 (int m, int d, int n)
{
long disp = (0x0000000F & (long)d);
Write_32 (R[n] + (disp << 2), R[m]);
PC += 2;
}
Example
mov.l r0,@(0xF,r1) ! Before execution: r0 = 0xFFFF7F80
! After execution: @(r1 + 60) = 0xFFFF7F80
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.l Rm,@(disp12,Rn)
Rm
0011 nnnn mmmm 00010010 dddddddddddd 1 0
Mov e Structure DataTransfers the source operand to the destination. This
instruction is ideal for data access in a structure or the stack.
Operation
void MOVLS12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
Write_32 (R[n] + (disp << 2), R[m]);
PC += 4;
}
Possible Exceptions
Data address error
mov.b @(R0,Rm),Rn
(R0
0000 nnnn mmmm 1100 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e DataTransfers the source operand to the destination.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVBL0 (int m, int n)
{
R[n] = Read_8 (R[m] + R[0]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else R[n] |= 0xFFFFFF00;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.w @(R0,Rm),Rn
(R0
0000 nnnn mmmm 1101 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e DataTransfers the source operand to the destination.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVWL0 (int m, int n)
{
R[n] = Read_16 (R[m] + R[0]);
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
}
Example
mov.w @(r0,r2),r1 ! Before execution: r2 = 0x00000004, r0 = 0x10000000
! After execution: r1 = @0x10000004
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.l @(R0,Rm),Rn
(R0
0000 nnnn mmmm 1110 LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVLL0 (int m, int n)
{
R[n] = Read_32 (R[m] + R[0]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.b Rm,@(R0,Rn)
Rm
0000 nnnn mmmm 0100 LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVBS0 (int m, int n)
{
Write_8 (R[n] + R[0], R[m]);
PC += 2;
}
Example
mov.b r1,@(r0,r2) ! Before execution: r2 = 0x00000004, r0 = 0x10000000
! After execution: r1 = @0x10000004
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.w Rm,@(R0,Rn)
Rm
0000 nnnn mmmm 0101 LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVWS0 (int m, int n)
{
Write_16 (R[n] + R[0], R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.l Rm,@(R0,Rn)
Rm
0000 nnnn mmmm 0110 LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e DataTransfers the source operand to the destination.
Operation
void MOVLS0 (int m, int n)
{
Write_32 (R[n] + R[0], R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.b @(disp,GBR),R0
(disp
11000100 dddddddd LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e Global DataTransfers the source operand to the destination.
The 8-bit displacement is only zero-extended, so a range up to +255 bytes can be
specified.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVBLG (int d)
{
unsigned int disp = (0x000000FF & d);
R[0] = Read_8 (GBR + disp);
if ((R[0] & 0x80) == 0)
R[0] &= 0x000000FF;
else
R[0] |= 0xFFFFFF00;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.w @(disp,GBR),R0
(disp
11000101 dddddddd LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e Global DataTransfers the source operand to the destination.
The 8-bit displacement is multiplied by two after zero-extension, enabling a
range up to +510 bytes to be specified.
The loaded data is sign-extended to 32 bit before being stored in the
destination register.
Operation
void MOVWLG (int d)
{
unsigned int disp = (0x000000FF & d);
R[0] = Read_16 (GBR + (disp << 1));
if ((R[0] & 0x8000) == 0)
R[0] &= 0x0000FFFF;
else
R[0] |= 0xFFFF0000;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.l @(disp,GBR),R0
(disp
11000110 dddddddd LS LS 1 1 1 1 1 1 1 1 1 2 2 1 2 1
Mov e Global DataTransfers the source operand to the destination.
The 8-bit displacement is multiplied by four after zero-extension, enabling a
range up to +1020 bytes to be specified.
Operation
void MOVLLG (int d)
{
unsigned int disp = (0x000000FF & d);
R[0] = Read_32 (GBR + (disp << 2));
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mov.b R0,@(disp,GBR)
R0
11000000 dddddddd LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e Global DataTransfers the source operand to the destination.
The 8-bit displacement is only zero-extended, so a range up to +255 bytes can be
specified.
Operation
void MOVBSG (int d)
{
unsigned int disp = (0x000000FF & d);
Write_8 (GBR + disp, R[0]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.w R0,@(disp,GBR)
R0
11000001 dddddddd LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e Global DataTransfers the source operand to the destination.
The 8-bit displacement is multiplied by two after zero-extension, enabling a
range up to +510 bytes to be specified.
Operation
void MOVWSG (int d)
{
unsigned int disp = (0x000000FF & d);
Write_16 (GBR + (disp << 1), R[0]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
mov.l R0,@(disp,GBR)
R0
11000010 dddddddd LS LS 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Mov e Global DataTransfers the source operand to the destination.
The 8-bit displacement is multiplied by four after zero-extension, enabling a
range up to +1020 bytes to be specified.
Operation
void MOVLSG (int d)
{
unsigned int disp = (0x000000FF & (long)d);
Write_32 (GBR + (disp << 2), R[0]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
movco.l R0,@Rn
LDST
0000 nnnn 01110011 LDST
CO 1 1
Mov e Co nditionalMOVCO is used in combination with MOVLI to realize an atomic read-modify-write
operation in a single processor.T bit. When the T bit
is set to 1, the value of R0 is stored at the address in Rm. If the T bit is
cleared to 0, the value is not stored at the address in Rm. Finally, the LDST
flag is cleared to 0. Since the LDST flag is cleared by an instruction or
exception, storage by the MOVCO instruction only proceeds when no interrupt or
exception has occurred between the execution of the MOVLI and MOVCO instructions.
Operation
void MOVCO (int n)
{
T = LDST;
if (T == 1)
Write_32 (R[n], R[0]);
LDST = 0;
PC += 2
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
movli.l @Rm,R0
1
0000 mmmm 01100011 CO 1 1
Mov e Li nkedMOVLI is used in combination with MOVCO to realize an atomic read-modify-write
operation in a single processor.T bit and does not proceed with storage.
Operation
void MOVLINK (int m)
{
LDST = 1;
R[0] = Read_32 (R[m]);
PC += 2
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
movua.l @Rm,R0
(Rm)
0100 mmmm 10101001 LS 2 2
Mov e U na lignedLoads the longword of data from the effective address indicated
by the contents of Rm in memory to R0. The address is not restricted to longword
boundaries address (4n). This instruction allows loading from
non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). Data address error
exceptions do not occur when access is to non-longword-boundary addresses
(4n + 1, 4n + 2, and 4n + 3).
Operation
void MOVUAL (int m)
{
Read_Unaligned_32 (R0, R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error (when the privileged area is accessed from user mode)
movua.l @Rm+,R0
(Rm)
0100 mmmm 11101001 LS 2 2
Mov e U na lignedLoads the longword of data from the effective address indicated
by the contents of Rm in memory to R0. The address is not restricted to longword
boundaries address (4n). This instruction allows loading from
non-longword-boundary addresses (4n + 1, 4n + 2, and 4n + 3). Data address error
exceptions do not occur when access is to non-longword-boundary addresses
(4n + 1, 4n + 2, and 4n + 3).
Operation
void MOVUALP (int m)
{
Read_Unaligned_32 (R0,R[m]);
if (m != 0)
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error (when the privileged area is accessed from user mode)
movml.l Rm,@-R15
R15−4
0100 mmmm 11110001 1-16 1-16
Mov e M ulti-register L ower partTransfers a source operand to a destination. This instruction performs transfer
between a number of general registers (R0 to Rn/Rm) not exceeding the specified
register number and memory with the contents of R15 as its address.
PR is transferred instead of R15. That is, when
nnnn(mmmm) = 1111 is specified, R0 to R14 and PR are the general registers
subject to transfer.
Operation
void MOVLMML (int m)
{
for (int i = m; i >= 0; i--)
{
if (i == 15)
Write_32 (R[15] - 4, PR);
else
Write_32 (R[15] - 4, R[i]);
R[15] -= 4;
}
PC += 2;
}
Possible Exceptions
Data address error
movml.l @R15+,Rn
(R15)
0100 nnnn 11110101 1-16 2-17
Mov e M ulti-register L ower partTransfers a source operand to a destination. This instruction performs transfer
between a number of general registers (R0 to Rn/Rm) not exceeding the specified
register number and memory with the contents of R15 as its address.
PR is transferred instead of R15. That is, when
nnnn(mmmm) = 1111 is specified, R0 to R14 and PR are the general registers
subject to transfer.
Operation
void MOVLPML (int n)
{
for (int i = 0; i <= n; i++)
{
if (i == 15)
PR = Read_32 (R[15]);
else
R[i] = Read_32 (R[15]);
R[15] += 4;
}
PC += 2;
}
Possible Exceptions
Data address error
movmu.l Rm,@-R15
R15
0100 mmmm 11110000 1-16 1-16
Mov e M ulti-register U pper partTransfers a source operand to a destination. This instruction performs transfer
between a number of general registers (Rn/Rm to R14, PR ) not lower than the
specified register number and memory with the contents of R15 as its address.
PR is transferred instead of R15.
Operation
void MOVLMMU (int m)
{
Write_32 (R[15] - 4, PR);
R[15] -= 4;
for (int i = 14; i >= m; i--)
{
Write_32 (R[15] - 4, R[i]);
R[15] -= 4;
}
PC += 2;
}
Possible Exceptions
Data address error
movmu.l @R15+,Rn
(R15)
0100 nnnn 11110100 1-16 2-17
Mov e M ulti-register U pper partTransfers a source operand to a destination. This instruction performs transfer
between a number of general registers (Rn/Rm to R14, PR ) not lower than the
specified register number and memory with the contents of R15 as its address.
PR is transferred instead of R15.
Operation
void MOVLPMU (int n)
{
for (int i = n; i <= 14; i++)
{
R[i] = Read_32 (R[15]);
R[15] += 4;
}
PR = Read_32 (R[15]);
R[15] += 4;
PC += 2;
}
Possible Exceptions
Data address error
movrt Rn
0000 nnnn 00111001 1 1
Mov e R everse T bitReverses the T bit and then stores the resulting value in general register Rn.
The value of Rn is 0 when T = 1 and 1 when T = 0.
Operation
void MOVRT (int n)
{
if (T == 1)
R[n] = 0x00000000;
else
R[n] = 0x00000001;
PC += 2;
}
movt Rn
T
0000 nnnn 00101001 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Mov e T BitStores the T bit in general register Rn.
The value of Rn is 1 when T = 1 and 0 when T = 0.
Operation
void MOVT (int n)
{
if (T == 1)
R[n] = 0x00000001;
else
R[n] = 0x00000000;
PC += 2;
}
Example
xor r2,r2 ! r2 = 0
cmp/pz r2 ! T = 1
movt r0 ! r0 = 1
clrt ! T = 0
movt r1 ! r1 = 0
nott
0000000001101000 1 1
Not T bitInverts the T bit, then stores the resulting value in the T bit.
Operation
void NOTT (void)
{
if (T == 1)
T = 0;
else
T = 1;
PC += 2;
}
swap.b Rm,Rn
Rm
0110 nnnn mmmm 1000 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Swap Register HalvesSwaps the upper and lower parts of the contents of general register Rm and
stores the result in Rn.
The 8 bits from bit 15 to bit 8 of Rm are swapped with the 8 bits from bit 7 to
bit 0. The upper 16 bits of Rm are transferred directly to the upper 16 bits of
Rn.
Operation
void SWAPB (int m, int n)
{
unsigned long temp0, temp1;
temp0 = R[m] & 0xFFFF0000;
temp1 = (R[m] & 0x000000FF) << 8;
R[n] = (R[m] & 0x0000FF00) >> 8;
R[n] = R[n] | temp1 | temp0;
PC += 2;
}
Example
swap.b r0,r1 ! Before execution: r0 = 0x12345678
! After execution: r1 = 0x12347856
swap.w Rm,Rn
Rm
0110 nnnn mmmm 1001 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Swap Register HalvesSwaps the upper and lower parts of the contents of general register Rm and
stores the result in Rn.
The 16 bits from bit 31 to bit 16 of Rm are swapped with the 16 bits from bit
15 to bit 0.
Operation
void SWAPW (int m, int n)
{
unsigned long temp;
temp = (R[m] >> 16) & 0x0000FFFF;
R[n] = R[m] << 16;
R[n] |= temp;
PC += 2;
}
Example
swap.w r0,r1 ! Before execution: r0 = 0x12345678
! After execution: r1 = 0x5678123
xtrct Rm,Rn
Rm:Rn middle 32 bits
0010 nnnn mmmm 1101 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Extr act
Extracts the middle 32 bits from the 64-bit contents of linked general registers
Rm and Rn, and stores the result in Rn.
Operation
void XTRCT (int m, int n)
{
unsigned long high = (R[m] << 16) & 0xFFFF0000;
unsigned long low = (R[n] >> 16) & 0x0000FFFF;
R[n] = high | low;
PC += 2;
}
Example
xtrct r0,r1 ! Before execution: r0 = 0x01234567, r1 = 0x89ABCDEF
! After execution: r1 = 0x456789AB
Bit Manipulation Instructions
band.b #imm3,@disp12,Rn
(imm of (disp
0011 nnnn 0 iii 10010100 dddddddddddd Result
3 3
B it And ANDs a specified bit in memory at the address indicated by (disp + Rn) with the
T bit, and stores the result in the T bit. The bit number is specified by 3-bit
immediate data. With this instruction, data is read from memory as a byte unit.
Operation
void BANDM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
long assignbit = (0x00000001 << imm) & temp;
if ((T == 0) || (assignbit == 0))
T = 0;
else
T = 1;
PC += 4;
}
Possible Exceptions
Data address error
bandnot.b #imm3,@(disp12,Rn)
0011 nnnn 0 iii 10011100 dddddddddddd Result
3 3
B it And Not ANDs the value obtained by inverting a specified bit of memory at the address
indicated by (disp + Rn) with the T bit, and stores the result in the T bit.
The bit number is specified by 3-bit immediate data. With this instruction, data
is read from memory as a byte unit.
Operation
void BANDNOTM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
long assignbit = (0x00000001 << imm) & temp;
if ((T == 1) && (assignbit == 0))
T = 1;
else
T = 0;
PC += 4;
}
Possible Exceptions
Data address error
bclr.b #imm3,@(disp12,Rn)
0
0011 nnnn 0 iii 10010000 dddddddddddd 3 2
B it Cl ear Clears a specified bit of memory at the address indicated by (disp + Rn).
The bit number is specified by 3-bit immediate data. After data is read from
memory as a byte unit, clearing of the specified bit is executed and the
resulting data is then written to memory as a byte unit.
Operation
void BCLRM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
temp &= (~(0x00000001 << imm));
Write_8 (R[n] + disp, temp);
PC += 4;
}
Possible Exceptions
Data address error
bclr #imm3,Rn
0
10000110 nnnn 0 iii 1 1
B it Cl ear Clears a specified bit of the LSB 8 bits of a general register Rn.
The bit number is specified by 3-bit immediate data.
Operation
void CLR (int i, int n)
{
long imm, temp;
imm = (0x00000007 & (long)i);
R[n] &= (~(0x00000001 << imm));
PC += 2;
}
bld.b #imm3,@(disp12,Rn)
(imm of (disp
0011 nnnn 0 iii 10010011 dddddddddddd Result
3 3
B it L oad Stores a specified bit of memory at the address indicated by (disp + Rn) in the
T bit. The bit number is specified by 3-bit immediate data. Data is read from
memory as a byte unit.
Operation
void BLDM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
long assignbit = (0x00000001 << imm) & temp;
if (assignbit == 0)
T = 0;
else
T = 1;
PC += 4;
}
Possible Exceptions
Data address error
bld #imm3,Rn
imm of Rn
10000111 nnnn 1 iii Result
1 1
B it L oad Stores a specified bit of the LSB 8 bits of a general register Rn in the T bit.
The bit number is specified by 3-bit immediate data.
Operation
void BLD (int i, int n)
{
long imm, assignbit;
imm = (0x00000007 & (long)i);
assignbit = (0x00000001 << imm) & R[n];
if (assignbit == 0)
T = 0;
else
T = 1;
PC += 2;
}
bldnot.b #imm3,@(disp12,Rn)
0011 nnnn 0 iii 10011011 dddddddddddd Result
3 3
B it L oad Not Inverts a specified bit of memory at the address indicated by (disp + Rn), and
stores the resulting value in the T bit. The bit number is specified by 3-bit
immediate data. Data is read from memory as a byte unit.
Operation
void BLDNOTM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
long assignbit = (0x00000001 << imm) & temp;
if (assignbit == 0)
T = 1;
else
T = 0;
PC += 4;
}
Possible Exceptions
Data address error
bor.b #imm3,@(disp12,Rn)
(imm of (disp
0011 nnnn 0 iii 10010101 dddddddddddd Result
3 3
B it O rORs a specified bit in memory at the address indicated by (disp + Rn) with the
T bit, and stores the result in the T bit. The bit number is specified by 3-bit
immediate data. Data is read from memory as a byte unit.
Operation
void BORM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
long assignbit = (0x00000001 << imm) & temp;
if ((T == 0) && (assignbit == 0))
T = 0;
else
T = 1;
PC += 4;
}
Possible Exceptions
Data address error
bornot.b #imm3,@(disp12,Rn)
0011 nnnn 0 iii 10011101 dddddddddddd Result
3 3
B it Or Not ORs the value obtained by inverting a specified bit of memory at the address
indicated by (disp + Rn) with the T bit, and stores the result in the T bit.
The bit number is specified by 3-bit immediate data. With this instruction,
data is read from memory as a byte unit.
Operation
void BORNOTM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
long assignbit = (0x00000001 << imm) & temp;
if ((T == 1) || (assignbit == 0))
T = 1;
else
T = 0;
PC += 4;
}
Possible Exceptions
Data address error
bset.b #imm3,@(disp12,Rn)
1
0011 nnnn 0 iii 10010001 dddddddddddd 3 2
B it Set Sets to 1 a specified bit of memory at the address indicated by (disp + Rn).
The bit number is specified by 3-bit immediate data. After data is read from
memory as a byte unit, the specified bit is set to 1, and the resulting data is
then written to memory as a byte unit.
Operation
void BSETM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
temp |= (0x00000001 << imm);
Write_8 (R[n] + disp, temp);
PC += 4;
}
Possible Exceptions
Data address error
bset #imm3,Rn
1
10000110 nnnn 1 iii 1 1
B it Set Sets to 1 a specified bit of the LSB 8 bits of a general register Rn. The bit
number is specified by 3-bit immediate data.
Operation
void BSET (int i, int n)
{
long imm, temp;
imm = (0x00000007 & (long)i);
R[n] |= (0x00000001 << imm);
PC += 2;
}
bst.b #imm3,@(disp12,Rn)
T
0011 nnnn 0 iii 10010010 dddddddddddd 3 2
B it St oreTransfers the contents of the T bit to a specified 1-bit location of memory at
the address indicated by (disp + Rn). The bit number is specified by 3-bit
immediate data. After data is read from memory as a byte unit, transfer from the
T bit to the specified bit is executed, and the resulting data is then written
to memory as a byte unit.
Operation
void BSTM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
if (T == 0)
temp &= (~(0x00000001 << imm));
else
temp |= (0x00000001 << imm);
Write_8 (R[n] + disp, temp);
PC += 4;
}
Possible Exceptions
Data address error
bst #imm3,Rn
T
10000111 nnnn 0 iii 1 1
B it St oreTransfers the contents of the T bit to a specified 1-bit location of the
LSB 8 bits of a general register Rn. The bit number is specified by 3-bit
immediate data.
Operation
void BST (int i, int n)
{
long disp, imm;
disp = (0x00000FFF & (long)d);
imm = (0x00000007 & (long)i);
if (T == 0)
R[n] &= (~(0x00000001 << imm));
else
R[n] |= (0x00000001 << imm);
PC += 2;
}
bxor.b #imm3,@(disp12,Rn)
(imm of (disp
0011 nnnn 0 iii 10010110 dddddddddddd Result
3 3
B it Ex clusive Or Exclusive-ORs a specified bit in memory at the address indicated by (disp + Rn)
with the T bit, and stores the result in the T bit. The bit number is specified
by 3-bit immediate data. With this instruction, data is read from memory as a
byte unit.
Operation
void BXORM (int d, int i, int n)
{
long disp = (0x00000FFF & (long)d);
long imm = (0x00000007 & (long)i);
long temp = Read_8 (R[n] + disp);
long assignbit = (0x00000001 << imm) & temp;
if (assignbit == 0)
{
if (T == 0)
T = 0;
else
T = 1;
}
else
{
if (T == 0)
T = 1;
else
T = 0;
}
PC += 4;
}
Possible Exceptions
Data address error
Arithmetic Operation Instructions
add Rm,Rn
Rn
0011 nnnn mmmm 1100 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Add BinaryAdds together the contents of general registers Rn and Rm and stores the
result in Rn.
Operation
void ADD (int m, int n)
{
R[n] += R[m];
PC += 2;
}
Example
add r0,r1 ! Before execution: r0 = 0x7FFFFFFF, r1 = 0x00000001
! After execution: r1 = 0x80000000
add #imm,Rn
Rn
0111 nnnn iiiiiiii EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Add BinaryAdds together the contents of general register Rn and the immediate value
and stores the result in Rn. The 8-bit immediate value is sign-extended to
32 bits, which allows it to be used for immediate subtraction or decrement
operations.
Operation
void ADDI (int i, int n)
{
if ((i & 0x80) == 0)
R[n] += (0x000000FF & (long)i);
else
R[n] += (0xFFFFFF00 | (long)i);
PC += 2;
}
Example
add #0x01,r2 ! Before execution: r2 = 0x00000000
! After execution: r2 = 0x00000001
add #0xFE,r3 ! Before execution: r3 = 0x00000001
! After execution: r3 = 0xFFFFFFFF
addc Rm,Rn
Rn
0011 nnnn mmmm 1110 Carry
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Add with C arryAdds together the contents of general registers Rn and Rm and the T bit, and
stores the result in Rn. A carry resulting from the operation is reflected in
the T bit. This instruction can be used to implement additions exceeding 32
bits.
Operation
void ADDC (int m, int n)
{
unsigned long tmp0, tmp1;
tmp1 = R[n] + R[m];
tmp0 = R[n];
R[n] = tmp1 + T;
if (tmp0>tmp1)
T = 1;
else
T = 0;
if (tmp1 > R[n])
T = 1;
PC += 2;
}
Example
clrt ! r0:r1 (64 bits) + r2:r3 (64 bits) = r0:r1 (64 bits)
ADDC r3 ,r1 ! Before execution: T = 0, r1 = 0x00000001, r3 = 0xFFFFFFFF
! After execution: T = 1, r1 = 0x00000000
ADDC r2 ,r0 ! Before execution: T = 1, r0 = 0x00000000, r2 = 0x00000000
! After execution: T = 0, r0 = 0x00000001
addv Rm,Rn
Rn
0011 nnnn mmmm 1111 Overflow
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Add with `V Flag` Overflow CheckAdds together the contents of general registers Rn and Rm and stores the result
in Rn. If overflow occurs, the T bit is set.
Operation
void ADDV (int m, int n)
{
long dest, src, ans;
if ((long)R[n] >= 0)
dest = 0;
else
dest = 1;
if ((long)R[m] >= 0)
src = 0;
else
src = 1;
src += dest;
R[n] += R[m];
if ((long)R[n] >= 0)
ans = 0;
else
ans = 1;
ans += dest;
if (src == 0 || src == 2)
{
if (ans == 1)
T = 1;
else
T = 0;
}
else
T = 0;
PC += 2;
}
Example
addv r0,r1 ! Before execution: r0 = 0x00000001, r1 = 0x7FFFFFFE, T = 0
! After execution: r1 = 0x7FFFFFFF, T = 0
addv r0,r1 ! Before execution: r0 = 0x00000002, r1 = 0x7FFFFFFE, T = 0
! After execution: r1 = 0x80000000, T = 1
cmp/eq #imm,R0
If R0
10001000 iiiiiiii Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If Eq ual ToCompares general register R0 and the sign-extended 8-bit immediate data and sets
the T bit if the values are equal. If they are not equal the T bit is cleared.
The contents of R0 are not changed.
Operation
void CMPIM (int i)
{
long imm;
if ((i & 0x80) == 0)
imm = (0x000000FF & (long i));
else
imm = (0xFFFFFF00 | (long i));
if (R[0] == imm)
T = 1;
else
T = 0;
PC += 2;
}
cmp/eq Rm,Rn
If Rn
0011 nnnn mmmm 0000 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If Eq ual ToCompares general registers Rn and Rm, and sets the T bit if they are equal.
The contents of Rn and Rm are not changed.
Operation
void CMPEQ (int m, int n)
{
if (R[n] == R[m])
T = 1;
else
T = 0;
PC += 2;
}
cmp/hs Rm,Rn
If Rn
0011 nnnn mmmm 0010 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If H igher or S ame (Unsigned Greater Than or Equal To)Compares general registers Rn and Rm, and sets the T bit if Rn is greater or
equal Rm. The values for the comparison are interpreted as unsigned integer
values. The contents of Rn and Rm are not changed.
Operation
void CMPHI (int m, int n)
{
if ((unsigned long)R[n] >= (unsigned long)R[m])
T = 1;
else
T = 0;
PC += 2;
}
cmp/ge Rm,Rn
If Rn
0011 nnnn mmmm 0011 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If Signed G reater Than or E qual ToCompares general registers Rn and Rm, and sets the T bit if Rn is greater or
equal Rm. The values for the comparison are interpreted as signed integer
values. The contents of Rn and Rm are not changed.
Operation
void CMPGE (int m, int n)
{
if ((long)R[n] >= (long)R[m])
T = 1;
else
T = 0;
PC += 2;
}
cmp/hi Rm,Rn
If Rn
0011 nnnn mmmm 0110 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If Hi gher (Unsigned Greater Than)Compares general registers Rn and Rm, and sets the T bit if Rn is greater Rm.
The values for the comparison are interpreted as unsigned integer values.
The contents of Rn and Rm are not changed.
Operation
void CMPHI (int m, int n)
{
if ((unsigned long)R[n] > (unsigned long)R[m])
T = 1;
else
T = 0;
PC += 2;
}
cmp/gt Rm,Rn
If Rn
0011 nnnn mmmm 0111 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If Signed G reater T hanCompares general registers Rn and Rm, and sets the T bit if Rn is greater Rm.
The values for the comparison are interpreted as signed integer values.
The contents of Rn and Rm are not changed.
Operation
void CMPGT (int m, int n)
{
if ((long)R[n] > (long)R[m])
T = 1;
else
T = 0;
PC += 2;
}
cmp/pl Rn
If Rn
0100 nnnn 00010101 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If Pl us (Signed Greater Than Zero)Compares general register Rn and sets the T bit if Rn is greater 0. The value
in Rn for the comparison is interpreted as signed integer. The contents of Rn
are not changed.
Operation
void CMPPL (int n)
{
if ((long)R[n] > 0)
T = 1;
else
T = 0;
PC += 2;
}
cmp/pz Rn
If Rn
0100 nnnn 00010001 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If P ositive or Z ero (Signed Greater Than or Equal To Zero)Compares general register Rn and sets the T bit if Rn is greater or equal 0.
The value in Rn for the comparison is interpreted as signed integer. The
contents of Rn are not changed.
Operation
void CMPPZ (int n)
{
if ((long)R[n] >= 0)
T = 1;
else
T = 0;
PC += 2;
}
cmp/str Rm,Rn
If Rn and Rm have an equal byte: 1
0010 nnnn mmmm 1100 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C omp are If Str ings EqualCompares general registers Rn and Rm, and sets the T bit if any of the 4 bytes
in Rn are equal to the corresponding byte in Rm. The contents of Rn and Rm are
not changed.
Note
This instruction can be used to speed up some string operations such as
finding the string length of a zero terminated string or string matching.
Operation
void CMPSTR (int m, int n)
{
unsigned long temp;
long HH, HL, LH, LL;
temp = R[n] ^ R[m];
HH = (temp & 0xFF000000) >> 24;
HL = (temp & 0x00FF0000) >> 16;
LH = (temp & 0x0000FF00) >> 8;
LL = temp & 0x000000FF;
HH = HH && HL && LH && LL;
if (HH == 0)
T = 1;
else
T = 0;
PC += 2;
}
Example
cmp/str r2,r3 ! r2 = "ABCD", r3 = "XYCZ"
bt target ! T = 1, so branch is taken.
clips.b Rn
If Rn
0100 nnnn 10010001 1 1
CLIP as S ignedDetermines saturation. Signed data is used with this instruction. The saturation
upper-limit value is stored in general register Rn if the contents of Rn exceed
the saturation upper-limit value, or the saturation lower-limit value is stored
in Rn if the contents of Rn are less than the saturation lower-limit value, and
the CS bit is set to 1.
The saturation upper-limit value is 0x0000007F (127).
The saturation lower-limit value is 0xFFFFFF80 (-128).
Note
The CS bit value does not change if the contents of general register Rn do not
exceed the saturation upper-limit value or are not less than the saturation
lower-limit value.
Operation
void CLIPSB (int n)
{
if (R[n] > 0x0000007F)
{
R[n] = 0x0000007F;
CS = 1;
}
else if (R[n] < 0xFFFFFF80)
{
R[n] = 0xFFFFFF80;
CS = 1;
}
PC += 2;
}
clips.w Rn
If Rn
0100 nnnn 10010101 1 1
CLIP as S ignedDetermines saturation. Signed data is used with this instruction. The saturation
upper-limit value is stored in general register Rn if the contents of Rn exceed
the saturation upper-limit value, or the saturation lower-limit value is stored
in Rn if the contents of Rn are less than the saturation lower-limit value, and
the CS bit is set to 1.
The saturation upper-limit value is 0x00007FFF (32767).
The saturation lower-limit value is 0xFFFF8000 (-32768).
Note
The CS bit value does not change if the contents of general register Rn do not
exceed the saturation upper-limit value or are not less than the saturation
lower-limit value.
Operation
void CLIPSW (int n)
{
if (R[n] > 0x00007FFF)
{
R[n] = 0x00007FFF;
CS = 1;
}
else if (R[n] < 0xFFFF8000)
{
R[n] = 0xFFFF8000;
CS = 1;
}
PC += 2;
}
clipu.b Rn
If Rn
0100 nnnn 10000001 1 1
CLIP as U nsignedDetermines saturation. Unsigned data is used with this instruction. If the
contents of general register Rn exceed the saturation value, the saturation
value is stored in Rn and the CS bit is set to 1.
The saturation value is 0x000000FF (255).
Note
The CS bit value does not change if the contents of general register Rn do not
exceed the saturation upper-limit value.
Operation
void CLIPUB (int n)
{
if (R[n] > 0x000000FF)
{
R[n] = 0x000000FF;
CS = 1;
}
PC += 2;
}
clipu.w Rn
If Rn
0100 nnnn 10000101 1 1
CLIP as U nsignedDetermines saturation. Unsigned data is used with this instruction. If the
contents of general register Rn exceed the saturation value, the saturation
value is stored in Rn and the CS bit is set to 1.
The saturation value is 0x0000FFFF (65535).
Note
The CS bit value does not change if the contents of general register Rn do not
exceed the saturation upper-limit value.
Operation
void CLIPUW (int n)
{
if (R[n] > 0x0000FFFF)
{
R[n] = 0x0000FFFF;
CS = 1;
}
PC += 2;
}
div0s Rm,Rn
MSB of Rn
0010 nnnn mmmm 0111 Result
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Div ide `Step 0 ` as S ignedPerforms initial settings for signed division. This instruction is followed by
a DIV1 instruction that executes 1-digit division, for example, and repeated
division steps are executed to find the quotient. See the description of the
DIV1 instruction for details.
Note
This instruction can also be used to compare the signs of Rm and Rn. If the
signs of Rm and Rn are equal, T will be set to 0. If the signs of Rm and Rn
are not equal, T will be set to 1.
Operation
void DIV0S (int m, int n)
{
if ((R[n] & 0x80000000) == 0)
Q = 0;
else
Q = 1;
if ((R[m] & 0x80000000) == 0)
M = 0;
else
M = 1;
T = ! (M == Q);
PC += 2;
}
div0u
0
0000000000011001 0
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Div ide `Step 0 ` as U nsignedPerforms initial settings for unsigned division. This instruction is followed by
a DIV1 instruction that executes 1-digit division, for example, and repeated
division steps are executed to find the quotient. See the description of the
DIV1 instruction for details.
Operation
void DIV0U (void)
{
M = Q = T = 0;
PC += 2;
}
div1 Rm,Rn
1
0011 nnnn mmmm 0100 Result
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Div ide 1 StepPerforms 1-digit division (1-step division) of the 32-bit contents of general
register Rn (dividend) by the contents of Rm (divisor).
The quotient is obtained by repeated execution of this instruction alone or in
combination with other instructions. The specified registers and the M , Q , and
T bits must not be modified during these repeated executions.
Q bit according
to whether the result is positive or negative.
remainder = dividend - (divisor × quotient)
Operation
void DIV1 (int m, int n)
{
unsigned long tmp0, tmp2;
unsigned char old_q, tmp1;
old_q = Q;
Q = (0x80000000 & R[n]) != 0;
tmp2 = R[m];
R[n] <<= 1;
R[n] |= (unsigned long)T;
if (old_q == 0)
{
if (M == 0)
{
tmp0 = R[n];
R[n] -= tmp2;
tmp1 = R[n] > tmp0;
if (Q == 0)
Q = tmp1;
else if (Q == 1)
Q = tmp1 == 0;
}
else if (M == 1)
{
tmp0 = R[n];
R[n] += tmp2;
tmp1 = R[n] < tmp0;
if (Q == 0)
Q = tmp1 == 0;
else if (Q == 1)
Q = tmp1;
}
}
else if (old_q == 1)
{
if (M == 0)
{
tmp0 = R[n];
R[n] += tmp2;
tmp1 = R[n] < tmp0;
if (Q == 0)
Q = tmp1;
else if (Q == 1)
Q = tmp1 == 0;
}
else if (M == 1)
{
tmp0 = R[n];
R[n] -= tmp2;
tmp1 = R[n] > tmp0;
if (Q == 0)
Q = tmp1 == 0;
else if (Q == 1)
Q = tmp1;
}
}
T = (Q == M);
PC += 2;
}
Example
! r1 (32 bits) / r0 (16 bits) = r1 (16 bits) (unsigned)
shll16 r0 ! Set divisor in upper 16 bits, clear lower 16 bits to 0
tst r0,r0 ! Check for division by zero
bt zero_div
cmp/hs r0,r1 ! Check for overflow
bt over_div
div0u ! Flag initialization
.rept 16
div1 r0,r1 ! Repeat 16 times
.endr
rotcl r1
extu.w r1,r1 ! r1 = quotient
- - - - - - - - - - - - - - - -
! r1:r2 (64 bits) / r0 (32 bits) = r2 (32 bits) (unsigned)
tst r0,r0 ! Check for division by zero
bt zero_div
cmp/hs r0,r1 ! Check for overflow
bt over_div
div0u ! Flag initialization
.rept 32
rotcl r2 ! Repeat 32 times
div1 r0,r1
.endr
rotcl r2 ! r2 = quotient
- - - - - - - - - - - - - - - -
! r1 (16 bits) / r0 (16 bits) = r1 (16 bits) (signed)
shll16 r0 ! Set divisor in upper 16 bits, clear lower 16 bits to 0
exts.w r1,r1 ! Dividend sign-extended to 32 bits
mov #0,r2
mov r1,r3
rotcl r3
subc r2,r1 ! If dividend is negative, subtract 1
div0s r0,r1 ! Flag initialization
.rept 16
div1 r0,r1 ! Repeat 16 times
.endr
exts.w r1,r1
rotcl r1 ! r1 = quotient (one's complement notation)
addc r2,r1 ! If MSB of quotient is 1, add 1 to convert to two's complement notation
exts.w r1,r1 ! r1 = quotient (two's complement notation)
- - - - - - - - - - - - - - - -
! r2 (32 bits) / r0 (32 bits) = r2 (32 bits) (signed)
mov r2,r3
rotcl r3
subc r1,r1 ! Dividend sign-extended to 64 bits (r1:r2)
mov #0,r3
subc r3,r2 ! If dividend is negative, subtract 1 to convert to one's complement notation
div0s r0,r1 ! Flag initialization
.rept 32
rotcl r2 ! Repeat 32 times
div1 r0,r1
.endr
rotcl r2 ! r2 = quotient (one's complement notation)
addc r3,r2 ! If MSB of quotient is 1, add 1 to convert to two's complement notation
! r2 = quotient (two's complement notation)
- - - - - - - - - - - - - - - -
! r4 (8 bits) / r5 (8 bits) = r0 (8 bits) (unsigned)
extu.b r4,r4 ! Optional, not needed if value is known to be zero extended.
extu.b r5,r5 ! Optional, not needed if value is known to be zero extended.
shll8 r5
div0u
.rept 8
div1 r5,r4 ! Repeat 8 times
.endr
rotcl r4
extu.b r4,r0
divs R0,Rn
Signed, Rn
0100 nnnn 10010100 36 36
Div ide as S ignedExecutes division of the 32-bit contents of a general register Rn (dividend) by
the contents of R0 (divisor). This instruction executes signed division and
finds the quotient only. A remainder operation is not provided. To obtain the
remainder, find the product of the divisor and the obtained quotient, and
subtract this value from the dividend. The sign of the remainder will be the
same as that of the dividend.
Note
An overflow exception will occur if the negative maximum value (0x00000000) is
divided by -1. If division by zero is performed a division by zero exception
will occur.
Operation
void DIVS (int n)
{
R[n] = R[n] / R[0];
PC += 2;
}
Possible Exceptions
Overflow exception
Division by zero exception
divu R0,Rn
Unsigned, Rn
0100 nnnn 10000100 36 36
Div ide as U nsignedExecutes division of the 32-bit contents of a general register Rn (dividend) by
the contents of R0 (divisor). This instruction executes unsigned division and
finds the quotient only. A remainder operation is not provided. To obtain the
remainder, find the product of the divisor and the obtained quotient, and
subtract this value from the dividend.
Note
A division by zero exception will occur if division by zero is performed.
Operation
void DIVU (int n)
{
R[n]= (unsigned long)R[n] / (unsigned long)R[0];
PC += 2;
}
Possible Exceptions
Division by zero exception
dmuls.l Rm,Rn
Signed, Rn
0011 nnnn mmmm 1101 CO EX 2 2 2 2 2 1 2-4 3 3 2-5 4/4 2
D ouble-length Mul tiply as S ignedPerforms 32-bit multiplication of the contents of general register Rn by the
contents of Rm, and stores the 64-bit result in the MACH and MACL registers.
The multiplication is performed as a signed arithmetic operation.
Note
On SH4, when MAC */MUL* is followed by an STS.L MAC *,@-Rn instruction, the
latency of MAC */MUL* is 5 cycles.
Operation
void DMULS (int m, int n)
{
unsigned long RnL, RnH, RmL, RmH, Res0, Res1, Res2;
unsigned long temp0, temp1, temp2, temp3;
long tempm, tempn, fnLmL;
tempn = (long)R[n];
tempm = (long)R[m];
if (tempn < 0)
tempn = 0 - tempn;
if (tempm < 0)
tempm = 0 - tempm;
if ((long)(R[n] ^ R[m]) < 0)
fnLmL = -1;
else
fnLmL = 0;
temp1 = (unsigned long)tempn;
temp2 = (unsigned long)tempm;
RnL = temp1 & 0x0000FFFF;
RnH = (temp1 >> 16) & 0x0000FFFF;
RmL = temp2 & 0x0000FFFF;
RmH = (temp2 >> 16) & 0x0000FFFF;
temp0 = RmL * RnL;
temp1 = RmH * RnL;
temp2 = RmL * RnH;
temp3 = RmH * RnH;
Res2 = 0;
Res1 = temp1 + temp2;
if (Res1 < temp1)
Res2 += 0x00010000;
temp1 = (Res1 << 16) & 0xFFFF0000;
Res0 = temp0 + temp1;
if (Res0 < temp0)
Res2++;
Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;
if (fnLmL < 0)
{
Res2 = ~Res2;
if (Res0 == 0)
Res2++;
else
Res0 = (~Res0) + 1;
}
MACH = Res2;
MACL = Res0;
PC += 2;
}
Example
dmuls.l r0,r1 ! Before execution: r0 = 0xFFFFFFFE, r1 = 0x00005555
! After execution: MACH = 0xFFFFFFFF, MACL = 0xFFFF5556
sts MACH,r0 ! Operation result (top)
sts MACL,r0 ! Operation result (bottom)
dmulu.l Rm,Rn
Unsigned, Rn
0011 nnnn mmmm 0101 CO EX 2 2 2 2 2 1 2-4 2 2 2-5 4/4 2
D ouble-length Mul tiply as U nsignedPerforms 32-bit multiplication of the contents of general register Rn by the
contents of Rm, and stores the 64-bit result in the MACH and MACL registers.
The multiplication is performed as an unsigned arithmetic operation.
Note
On SH4, when MAC */MUL* is followed by an STS.L MAC *,@-Rn instruction, the
latency of MAC */MUL* is 5 cycles.
Operation
void DMULU (int m, int n)
{
unsigned long RnL, RnH, RmL, RmH, Res0, Res1, Res2;
unsigned long temp0, temp1, temp2, temp3;
RnL = R[n] & 0x0000FFFF;
RnH = (R[n] >> 16) & 0x0000FFFF;
RmL = R[m] & 0x0000FFFF;
RmH = (R[m] >> 16) & 0x0000FFFF;
temp0 = RmL * RnL;
temp1 = RmH * RnL;
temp2 = RmL * RnH;
temp3 = RmH * RnH;
Res2 = 0
Res1 = temp1 + temp2;
if (Res1 < temp1)
Res2 += 0x00010000;
temp1 = (Res1 << 16) & 0xFFFF0000;
Res0 = temp0 + temp1;
if (Res0 < temp0)
Res2++;
Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;
MACH = Res2;
MACL = Res0;
PC += 2;
}
Example
dmulu.l r0,r1 ! Before execution: r0 = 0xFFFFFFFE, r1 = 0x00005555
! After execution: MACH = 0xFFFFFFFF, MACL = 0xFFFF5556
sts MACH,r0 ! Operation result (top)
sts MACL,r0 ! Operation result (bottom
dt Rn
Rn
0100 nnnn 00010000 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D ecrement and T estDecrements the contents of general register Rn by 1 and compares the result
with zero. If the result is zero, the T bit is set to 1.
If the result is nonzero, the T bit is cleared to 0.
Operation
void DT (int n)
{
R[n]--;
if (R[n] == 0)
T = 1;
else T = 0;
PC += 2;
}
Example
mov #4,r4 ! Set loop count
loop:
add r0,r1
dt r5 ! Decrement r5 value and check for 0.
bf loop ! if T = 0 branch to loop
! (in this example, 4 loop iterations are executed)
exts.b Rm,Rn
Rm sign
0110 nnnn mmmm 1110 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Ext end as S ignedSign-extends the contents of general register Rm and stores the result in Rn.
The value of Rm bit 7 is transferred to Rn bits 8 to 31.
Operation
void EXTSB (int m, int n)
{
R[n] = R[m];
if ((R[m] & 0x00000080) == 0)
R[n] & = 0x000000FF;
else
R[n] |= 0xFFFFFF00;
PC += 2;
}
Example
exts.b r0,r1 ! Before execution: r0 = 0x00000080
! After execution: r1 = 0xFFFFFF80
exts.w Rm,Rn
Rm sign
0110 nnnn mmmm 1111 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Ext end as S ignedSign-extends the contents of general register Rm and stores the result in Rn.
The value of Rm bit 15 is transferred to Rn bits 16 to 31.
Operation
void EXTSW (int m, int n)
{
R[n] = R[m];
if ((R[m] & 0x00008000) == 0)
R[n] & = 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
}
Example
exts.w r0,r1 ! Before execution: r0 = 0x00008000
! After execution: r1 = 0xFFFF8000
extu.b Rm,Rn
Rm zero
0110 nnnn mmmm 1100 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Ext end as U nsignedZero-extends the contents of general register Rm and stores the result in Rn.
0 is transferred to Rn bits 8 to 31.
Operation
void EXTUB (int m, int n)
{
R[n] = R[m];
R[n] &= 0x000000FF;
PC += 2;
}
Example
extu.b r0,r1 ! Before execution: r0 = 0xFFFFFF80
! After execution: r1 = 0x00000080
extu.w Rm,Rn
Rm zero
0110 nnnn mmmm 1101 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Ext end as U nsignedZero-extends the contents of general register Rm and stores the result in Rn.
0 is transferred to Rn bits 16 to 31.
Operation
void EXTUW (int m, int n)
{
R[n] = R[m];
R[n] &= 0x0000FFFF;
PC += 2;
}
Example
extu.w r0,r1 ! Before execution: r0 = 0xFFFF8000
! After execution: r1 = 0x00008000
mac.l @Rm+,@Rn+
Signed, (Rn)
0000 nnnn mmmm 1111 CO CO 2 4 4 2 2 2 2-4 5 5 2-5 2/4 5
M ultiply and Ac cumulatePerforms signed multiplication of the 32-bit operands whose addresses are the
contents of general registers Rm and Rn, adds the 64-bit result to the MAC
register contents, and stores the result in the MAC register.
Operands Rm and Rn are each incremented by 4 each time they are read.
S bit is cleared to 0, the 64-bit result is stored in the coupled MACH
and MACL registers.
S is set to 1, addition to the MAC register is a saturation operation
of 48 bits starting from the LSB . For the saturation operation, only the lower
48 bits of the MACL register are enabled and the result is limited to a range
of 0xFFFF800000000000 (minimum) and 0x00007FFFFFFFFFFF (maximum).
Note
On SH4, when MAC */MUL* is followed by an STS.L MAC *,@-Rn instruction, the
latency of MAC */MUL* is 5 cycles. In the case of consecutive executions of
MAC .W/MAC .L, the latency is decreased to 2 cycles.
Operation
void MACL (int m, int n)
{
unsigned long RnL, RnH, RmL, RmH, Res0, Res1, Res2;
unsigned long temp0, temp1, temp2, temp3;
long tempm, tempn, fnLmL;
tempn = Read_32 (R[n]);
R[n] += 4;
tempm = Read_32 (R[m]);
R[m] += 4;
if ((long)(tempn ^ tempm) < 0)
fnLmL = -1;
else
fnLmL = 0;
if (tempn < 0)
tempn = 0 - tempn;
if (tempm < 0)
tempm = 0 - tempm;
temp1 = (unsigned long)tempn;
temp2 = (unsigned long)tempm;
RnL = temp1 & 0x0000FFFF;
RnH = (temp1 >> 16) & 0x0000FFFF;
RmL = temp2 & 0x0000FFFF;
RmH = (temp2 >> 16) & 0x0000FFFF;
temp0 = RmL * RnL;
temp1 = RmH * RnL;
temp2 = RmL * RnH;
temp3 = RmH * RnH;
Res2 = 0;
Res1 = temp1 + temp2;
if (Res1 < temp1)
Res2 += 0x00010000;
temp1 = (Res1 << 16) & 0xFFFF0000;
Res0 = temp0 + temp1;
if (Res0 < temp0)
Res2++;
Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3;
if(fnLmL < 0)
{
Res2 = ~Res2;
if (Res0 == 0)
Res2++;
else
Res0 = (~Res0) + 1;
}
if (S == 1)
{
Res0 = MACL + Res0;
if (MACL > Res0)
Res2++;
Res2 += MACH & 0x0000FFFF;
if (((long)Res2 < 0) && (Res2 < 0xFFFF8000))
{
Res2 = 0xFFFF8000;
Res0 = 0x00000000;
}
if (((long)Res2 > 0) && (Res2 > 0x00007FFF))
{
Res2 = 0x00007FFF;
Res0 = 0xFFFFFFFF;
}
MACH = (Res2 & 0x0000FFFF) | (MACH & 0xFFFF0000);
MACL = Res0;
}
else
{
Res0 = MACL + Res0;
if (MACL > Res0)
Res2 ++;
Res2 += MACH;
MACH = Res2;
MACL = Res0;
}
PC += 2;
}
Example
mova TBLM,r0 ! Table address
mov r0,r1
mova TBLN,r0 ! Table address
clrmac ! MAC register initialization
mac.l @r0+,@r1+
mac.l @r0+,@r1+
sts MACL,r0 ! Store result into r0
.align 2
TBLM: .data.l 0x1234ABCD
.data.l 0x5678EF01
TBLN: .data.l 0x0123ABCD
.data.l 0x4567DEF0
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mac.w @Rm+,@Rn+
Signed, (Rn)
0100 nnnn mmmm 1111 CO CO 2 2 3 3 2 2 2 2-3 2-3 4 4 2-5 2/4 4
M ultiply and Ac cumulatePerforms signed multiplication of the 16-bit operands whose addresses are the
contents of general registers Rm and Rn, adds the 32-bit result to the MAC
register contents, and stores the result in the MAC register.
Operands Rm and Rn are each incremented by 2 each time they are read.
S bit is 0, a 16 × 16 + 64 → 64-bit multiply-and-accumulate operation
is performed, and the 64-bit result is stored in the linked MACH and MACL
registers.
S bit is 1, a 16 × 16 + 32 → 32-bit multiply-and-accumulate operation is
performed, and the addition to the MAC register contents is a saturation
operation. In a saturation operation, only the MACL register is valid, and the
result range is limited to 0x80000000 (minimum value) to 0x7FFFFFFF
(maximum value). If overflow occurs, the LSB of the MACH register is set to 1.
0x80000000 (minimum value) is stored in the MACL register if the result
overflows in the negative direction, and 0x7FFFFFFF (maximum value) is stored
if the result overflows in the positive direction
Note
When the S bit is 0, the SH2 and SH-DSP CPU perform a 16 × 16 + 64 → 64 bit
multiply and accumulate operation and the SH1 CPU performs a 16 × 16 + 42 →
42 bit multiply and accumulate operation.
MAC */MUL* is followed by an STS.L MAC *,@-Rn instruction, the
latency of MAC */MUL* is 5 cycles. In the case of consecutive executions of
MAC .W/MAC .L, the latency is decreased to 2 cycles.
Operation
void MACW (int m, int n)
{
long tempm, tempn, dest, src, ans;
unsigned long templ;
tempn = Read_16 (R[n]);
R[n] += 2;
tempm = Read_16 (R[m]);
R[m] += 2;
templ = MACL;
tempm = ((long)(short)tempn * (long)(short)tempm);
if ((long)MACL >= 0)
dest = 0;
else
dest = 1;
if ((long)tempm >= 0)
{
src = 0;
tempn = 0;
}
else
{
src = 1;
tempn = 0xFFFFFFFF;
}
src += dest;
MACL += tempm;
if ((long)MACL >= 0)
ans = 0;
else
ans = 1;
ans += dest;
if (S == 1)
{
if (ans == 1)
{
#if SH1
if (src == 0 || src == 2)
MACH |= 0x00000001;
#endif
if (src == 0)
MACL = 0x7FFFFFFF;
if (src == 2)
MACL = 0x80000000;
}
}
else
{
MACH += tempn;
if (templ > MACL)
MACH += 1;
#if SH1
if ((MACH & 0x00000200) == 0)
MACH &= 0x000003FF;
else
MACH |= 0xFFFFFC00;
#endif
}
PC += 2;
}
Example
mova TBLM,r0 ! Table address
mov r0,r1
mova TBLN,r0 ! Table address
clrmac ! MAC register initialization
mac.w @r0+,@r1+
mac.w @r0+,@r1+
sts MACL,r0 ! Store result into r0
.align 2
TBLM: .data.w 0x1234
.data.w 0x5678
TBLN: .data.w 0x0123
.data.w 0x4567
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
mul.l Rm,Rn
Rn
0000 nnnn mmmm 0111 CO EX 2 2 2 2 2 1 2-4 3 3 2-4 4/4 2
Mul tiplyPerforms 32-bit multiplication of the contents of general registers Rn and Rm,
and stores the lower 32 bits of the result in the MACL register. The contents
of MACH are not changed.
Note
On SH4, when MAC */MUL* is followed by an STS.L MAC *,@-Rn instruction, the
latency of MAC */MUL* is 5 cycles.
Operation
void MULL (int m, int n)
{
MACL = R[n] * R[m];
PC += 2;
}
Example
mull r0,r1 ! Before execution: r0 = 0xFFFFFFFE, r1 = 0x00005555
! After execution: MACL = 0xFFFF5556
sts MACL,r0 ! Operation result
mulr R0,Rn
R0
0100 nnnn 10000000 2 4
Mul tiply to R egisterPerforms 32-bit multiplication of the contents of general register R0 by Rn,
and stores the lower 32 bits of the result in general register Rn.
Operation
void MULR (int n)
{
R[n] = R[0] * R[n];
PC += 2;
}
muls.w Rm,Rn
Signed, Rn
0010 nnnn mmmm 1111 CO EX 2 2 1 1 2 2 1 1-3 1-3 2 2 1-3 4/4 1
Mul tiply as S igned [W ord]Performs 16-bit multiplication of the contents of general registers Rn and Rm,
and stores the 32-bit result in the MACL register. The multiplication is
performed as a signed arithmetic operation. The contents of MACH are not
changed.
Note
On SH4, when MAC */MUL* is followed by an STS.L MAC *,@-Rn instruction, the
latency of MAC */MUL* is 5 cycles.
Operation
void MULS (int m, int n)
{
MACL = ((long)(short)R[n] * (long)(short)R[m]);
PC += 2;
}
Example
muls r0,r1 ! Before execution: r0 = 0xFFFFFFFE, r1 = 0x00005555
! After execution: MACL = 0xFFFF5556
sts MACL,r0 ! Operation result
mulu.w Rm,Rn
Unsigned, Rn
0010 nnnn mmmm 1110 CO EX 2 2 1 1 2 2 1 1-3 1-3 2 2 1-3 4/4 1
Mul tiply as U nsigned [W ord]Performs 16-bit multiplication of the contents of general registers Rn and Rm,
and stores the 32-bit result in the MACL register. The multiplication is
performed as an unsigned arithmetic operation. The contents of MACH are not
changed.
Note
On SH4, when MAC */MUL* is followed by an STS.L MAC *,@-Rn instruction, the
latency of MAC */MUL* is 5 cycles.
Operation
void MULU (int m, int n)
{
MACL = ((unsigned long)(unsigned short)R[n]* (unsigned long)(unsigned short)R[m];
PC += 2;
}
Example
mulu r0,r1 ! Before execution: r0 = 0x00000002, r1 = 0xFFFFAAAA
! After execution: MACL = 0x00015554
sts MACL,r0 ! Operation result
neg Rm,Rn
0
0110 nnnn mmmm 1011 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Neg ateFinds the two's complement of the contents of general register Rm and stores
the result in Rn. That is, it subtracts Rm from 0 and stores the result in Rn.
Operation
void NEG (int m, int n)
{
R[n] = 0 - R[m];
PC += 2;
}
Example
neg r0,r1 ! Before execution: r0 = 0x00000001
! After execution: r1 = 0xFFFFFFFF
negc Rm,Rn
0 − Rm
0110 nnnn mmmm 1010 Borrow
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Neg ate with C arrySubtracts the contents of general register Rm and the T bit from 0 and stores
the result in Rn. A borrow resulting from the operation is reflected in the
T bit. This instruction can be used for sign inversion of a value exceeding
32 bits.
Note
This instruction can also be used to efficiently store the reversed T bit value
in a general register, if the MOVRT instruction is not available.
Operation
void NEGC (int m, int n)
{
unsigned long temp;
temp = 0 - R[m];
R[n] = temp - T;
if (0 < temp)
T = 1;
else
T = 0;
if (temp < R[n])
T = 1;
PC += 2;
}
Example
! Sign inversion of r0:r1 (64 bits)
clrt
negc r1,r1 ! Before execution: r1 = 0x00000001, T = 0
! After execution: r1 = 0xFFFFFFFF, T = 1
negc r0,r0 ! Before execution: r0 = 0x00000000, T = 1
! After execution: r0 = 0xFFFFFFFF, T = 1
- - - - - - - - - - - - - - - -
! Store reversed T bit in r0
mov #-1,r1
negc r1,r0 ! r0 = 0 - (-1) - T
! r0 = 1 - T
! Notice that T bit will be modified by the negc operation.
! In this case, T will be always set to 1.
sub Rm,Rn
Rn
0011 nnnn mmmm 1000 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sub tract BinarySubtracts the contents of general register Rm from the contents of general
register Rn and stores the result in Rn. For immediate data subtraction,
ADD #imm,Rn should be used.
Operation
void SUB (int m, int n)
{
R[n] -= R[m];
PC += 2;
}
Example
sub r0,r1 ! Before execution: r0 = 0x00000001, r1 = 0x80000000
! After execution: r1 = 0x7FFFFFFF
subc Rm,Rn
Rn − Rm
0011 nnnn mmmm 1010 Borrow
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sub tract with C arrySubtracts the contents of general register Rm and the T bit from the contents of
general register Rn, and stores the result in Rn. A borrow resulting from the
operation is reflected in the T bit. This instruction is used for subtractions
exceeding 32 bits.
Note
This instruction can also be used to store the T bit to all the bits of a
general register.
Operation
void SUBC (int m, int n)
{
unsigned long tmp0, tmp1;
tmp1 = R[n] - R[m];
tmp0 = R[n];
R[n] = tmp1 - T;
if (tmp0 < tmp1)
T = 1;
else
T = 0;
if (tmp1 < R[n])
T = 1;
PC += 2;
}
Example
! r0:r1(64 bits) - r2:r3(64 bits) = r0:r1(64 bits)
clrt
subc r3,r1 ! Before execution: T = 0, r1 = 0x00000000, r3 = 0x00000001
! After execution: T = 1, r1 = 0xFFFFFFFF
subc r2,r0 ! Before execution: T = 1, r0 = 0x00000000, r2 = 0x00000000
! After execution: T = 1, r0 = 0xFFFFFFFF
- - - - - - - - - - - - - - - -
! Store T bit to all bits of r0
subc r0,r0 ! r0 = r0 - r0 - T
! r0 = 0 - T
! Notice that the T bit is modified by the subc operation.
subv Rm,Rn
Rn
0011 nnnn mmmm 1011 Underflow
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sub tract with `V Flag` Underflow CheckSubtracts the contents of general register Rm from the contents of general
register Rn, and stores the result in Rn. If underflow occurs, the T bit is set.
Operation
void SUBV (int m, int n)
{
long dest, src, ans;
if ((long)R[n] >= 0)
dest = 0;
else
dest = 1;
if ((long)R[m] >= 0)
src = 0;
else
src = 1;
src += dest;
R[n] -= R[m];
if ((long)R[n] >= 0)
ans = 0;
else
ans = 1;
ans += dest;
if (src == 1)
{
if (ans == 1)
T = 1;
else
T = 0;
}
else
T = 0;
PC += 2;
}
Example
subv r0,r1 ! Before execution: r0 = 0x00000002, r1 = 0x80000001
! After execution: r1 = 0x7FFFFFFF, T = 1
subv r2,r3 ! Before execution: r2 = 0xFFFFFFFE, r3 = 0x7FFFFFFE
! After execution: r3 = 0x80000000, T = 1
Logic Operation Instructions
and Rm,Rn
Rn
0010 nnnn mmmm 1001 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical And
ANDs the contents of general registers Rn and Rm and stores the result in Rn.
Operation
void AND (int m, int n)
{
R[n] &= R[m];
PC += 2;
}
Example
and r0,r1 ! Before execution: r0 = 0xAAAAAAAA, r1 = 0x55555555
! After execution: r1 = 0x00000000
and #imm,R0
R0
11001001 iiiiiiii EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical And
ANDs the contents of general register R0 and the zero-extended immediate value
and stores the result in R0.
Note
Since the 8-bit immediate value is zero-extended, the upper 24 bits of R0 are
always cleared to zero.
Operation
void ANDI (int i)
{
R[0] &= (0x000000FF & (long)i);
PC += 2;
}
Example
and #0x0F,r0 ! Before execution: r0 = 0xFFFFFFFF
! After execution: r0 = 0x0000000F
and.b #imm,@(R0,GBR)
(R0
11001101 iiiiiiii CO CO 2 2 3 3 2 4 3 3 3 2 2 3 4 3
Logical And
ANDs the contents of the memory byte indicated by the indirect GBR address with
the immediate value and writes the result back to the memory byte.
Operation
void ANDM (long i)
{
long temp = Read_8 (GBR + R[0]);
temp &= 0x000000FF & (long)i;
Write_8 (GBR + R[0], temp);
PC += 2;
}
Example
and.b #0x80,@(r0,GBR) ! Before execution: @(r0,GBR) = 0xA5
! After execution: @(r0,GBR) = 0x80
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
Exceptions are checked taking a data access by this instruction as a byte load
and a byte store.
not Rm,Rn
0110 nnnn mmmm 0111 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical Not Complement
Finds the one's complement of the contents of general register Rm and stores
the result in Rn. That is, it inverts the Rm bits and stores the result in Rn.
Operation
void NOT (int m, int n)
{
R[n] = ~R[m];
PC += 2;
}
Example
not r0,r1 ! Before execution: r0 = 0xAAAAAAAA
! After execution: r1 = 0x55555555
or Rm,Rn
Rn
0010 nnnn mmmm 1011 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical Or
ORs the contents of general registers Rn and Rm and stores the result in Rn.
Operation
void OR (int m, int n)
{
R[n] |= R[m];
PC += 2;
}
Example
or r0,r1 ! Before execution: r0 = 0xAAAA5555, r1 = 0x55550000
! After execution: r1 = 0xFFFF5555
or #imm,R0
R0
11001011 iiiiiiii EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical Or
ORs the contents of general register R0 and the zero-extended immediate value
and stores the result in R0.
Note
Since the 8-bit immediate value is zero-extended, the upper 24 bits of R0 are
not modified.
Operation
void ORI (int i)
{
R[0] |= (0x000000FF & (long)i);
PC += 2;
}
Example
or #0xF0,r0 ! Before execution: r0 = 0x00000008
! After execution: r0 = 0x000000F8
or.b #imm,@(R0,GBR)
(R0
11001111 iiiiiiii CO CO 2 2 3 3 2 4 3 3 3 2 2 3 4 3
Logical Or
ORs the contents of the memory byte indicated by the indirect GBR address with
the immediate value and writes the result back to the memory byte.
Operation
void ORM (int i)
{
long temp = Read_8 (GBR + R[0]);
temp |= (0x000000FF & (long)i);
Write_8 (GBR + R[0], temp);
PC += 2;
}
Example
or.b #0x50,@(r0,GBR) ! Before execution: @(r0,GBR) = 0xA5
! After execution: @(r0,GBR) = 0xF5
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
Exceptions are checked taking a data access by this instruction as a byte load
and a byte store.
tas.b @Rn
If (Rn)
0100 nnnn 00011011 Result
CO CO 2 2 3 3 2 5 4 4 4 3 3 3/4 5 4
T est a nd S etReads byte data from the address specified by general register Rn, and sets the
T bit to 1 if the data is 0, or clears the T bit to 0 if the data is not 0.
Then, data bit 7 is set to 1, and the data is written to the address specified
by Rn. During this operation, the bus is not released.
V bit
to 0). If there is a cache hit and the corresponding cache block is clean (U bit
= 0), the cache block is simply invalidated (by clearing the V bit to 0). A
purge is not executed in the event of a cache miss, or if the accessed memory
location is non-cacheable.
Note
The two TAS.B memory accesses are executed automatically. Another memory access
is not executed between the two TAS.B accesses.
Operation
void TAS (int n)
{
int temp = Read_8 (R[n]); // Bus Lock
if (temp == 0)
T = 1;
else
T = 0;
temp |= 0x00000080;
Write_8 (R[n], temp); // Bus unlock
PC += 2;
}
Example
_LOOP: tas.b @r7 ! r7 = 1000
bf _LOOP ! Loops until data in address 1000 is 0
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
Exceptions are checked taking a data access by this instruction as a byte load
and a byte store.
tst Rm,Rn
If Rn
0010 nnnn mmmm 1000 Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical T est
ANDs the contents of general registers Rn and Rm, and sets the T bit if the
result is zero. If the result is nonzero, the T bit is cleared. The contents of
Rn are not changed.
Operation
void TST (int m, int n)
{
if ((R[n] & R[m]) == 0)
T = 1;
else
T = 0;
PC += 2;
}
Example
tst r0,r0 ! Before execution: r0 = 0x00000000
! After execution: T = 1
tst #imm,R0
If R0
11001000 iiiiiiii Result
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical T est
ANDs the contents of general register R0 and the zero-extended immediate value
and sets the T bit if the result is zero. If the result is nonzero, the T bit
is cleared. The contents of Rn are not changed.
Note
Since the 8-bit immediate value is zero-extended, this instruction can only be
used to test the lower 8 bits of R0.
Operation
void TSTI (int i)
{
long temp = R[0] & (0x000000FF & (long)i);
if (temp == 0)
T = 1;
else
T = 0;
PC += 2;
}
Example
tst #0x80,r0 ! Before execution: r0 = 0xFFFFFF7F
! After execution: T = 1
tst.b #imm,@(R0,GBR)
If (R0
11001100 iiiiiiii Result
CO CO 2 2 3 3 2 3 3 3 3 3 3 3 3 3
Logical T est
ANDs the contents of the memory byte indicated by the indirect GBR address with
the zero-extended immediate value and sets the T bit if the result is zero.
If the result is nonzero, the T bit is cleared.
The contents of the memory byte are not changed.
Operation
void TSTM (int i)
{
long temp = Read_8 (GBR + R[0]);
temp &= (0x000000FF & (long)i);
if (temp == 0)
T = 1;
else
T = 0;
PC += 2;
}
Example
tst.b #0xA5,@(r0,GBR) ! Before execution: @(r0,GBR) = 0xA5
! After execution: T = 0
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Exceptions are checked taking a data access by this instruction as a byte load
and a byte store.
xor Rm,Rn
Rn
0010 nnnn mmmm 1010 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical Ex clusive Or
XORs the contents of general registers Rn and Rm and stores the result in Rn.
Operation
void XOR (long m, long n)
{
R[n] ^= R[m];
PC += 2;
}
Example
xor r0,r1 ! Before execution: r0 = 0xAAAAAAAA, r1 = 0x55555555
! After execution: r1 = 0xFFFFFFFF
xor #imm,R0
R0
11001010 iiiiiiii EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logical Ex clusive Or
XORs the contents of general register R0 and the zero-extended immediate value
and stores the result in R0.
Note
Since the 8-bit immediate value is zero-extended, the upper 24 bits of R0 are
not modified.
Operation
void XORI (int i)
{
R[0] ^= (0x000000FF & (long)i);
PC += 2;
}
Example
xor #0xF0,r0 ! Before execution: r0 = 0xFFFFFFFF
! After execution: r0 = 0xFFFFFF0F
xor.b #imm,@(R0,GBR)
(R0
11001110 iiiiiiii CO CO 2 2 3 3 2 4 3 2 2 3 3 2 4 3
Logical Ex clusive Or
XORs the contents of the memory byte indicated by the indirect GBR address with
the immediate value and writes the result back to the memory byte.
Operation
void XORM (int i)
{
int temp = Read_8 (GBR + R[0]);
temp ^= (0x000000FF & (long)i);
Write_8 (GBR + R[0], temp);
PC += 2;
}
Example
xor.b #0xA5,@(r0,GBR) ! Before execution: @(r0,GBR) = 0xA5
! After execution: @(r0,GBR) = 0x00
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
Exceptions are checked taking a data access by this instruction as a byte load
and a byte store.
Shift Instructions
rotcl Rn
T
0100 nnnn 00100100 MSB
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Rot ate with C arry L eftRotates the contents of general register Rn one bit to the left through the
T bit, and stores the result in Rn. The bit rotated out of the operand is
transferred to the T bit.
Operation
void ROTCL (int n)
{
long temp;
if ((R[n] & 0x80000000) == 0)
temp = 0;
else
temp = 1;
R[n] <<= 1;
if (T == 1)
R[n] |= 0x00000001;
else
R[n] &= 0xFFFFFFFE;
if (temp == 1)
T = 1;
else
T = 0;
PC += 2;
}
Example
rotcl r0 ! Before execution: r0 = 0x80000000, T = 0
! After execution: r0 = 0x00000000, T = 1
rotcr Rn
T
0100 nnnn 00100101 LSB
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Rot ate with C arry R ightRotates the contents of general register Rn one bit to the right through the
T bit, and stores the result in Rn. The bit rotated out of the operand is
transferred to the T bit.
Operation
void ROTCR (int n)
{
long temp;
if ((R[n] & 0x00000001) == 0)
temp = 0;
else
temp = 1;
R[n] >>= 1;
if (T == 1)
R[n] |= 0x80000000;
else
R[n] &= 0x7FFFFFFF;
if (temp == 1)
T = 1;
else
T = 0;
PC += 2;
}
Example
rotcr r0 ! Before execution: r0 = 0x00000001, T = 1
! After execution: r0 = 0x80000000, T = 1
rotl Rn
T
0100 nnnn 00000100 MSB
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Rot ate L eftRotates the contents of general register Rn one bit to the left, and stores the
result in Rn. The bit rotated out of the operand is transferred to the T bit.
Operation
void ROTL (int n)
{
if ((R[n] & 0x80000000) == 0)
T = 0;
else
T = 1;
R[n] <<= 1;
if (T == 1)
R[n] |= 0x00000001;
else
R[n] &= 0xFFFFFFFE;
PC += 2;
}
Example
rotl r0 ! Before execution: r0 = 0x80000000, T = 0
! After execution: r0 = 0x00000001, T = 1
rotr Rn
LSB
0100 nnnn 00000101 LSB
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Rot ate R ightRotates the contents of general register Rn one bit to the right, and stores the
result in Rn. The bit rotated out of the operand is transferred to the T bit.
Operation
void ROTR (int n)
{
if ((R[n] & 0x00000001) == 0)
T = 0;
else
T = 1;
R[n] >>= 1;
if (T == 1)
R[n] |= 0x80000000;
else
R[n] &= 0x7FFFFFFF;
PC += 2;
}
Example
rotr r0 ! Before execution: r0 = 0x00000001, T = 0
! After execution: r0 = 0x80000000, T = 1
shad Rm,Rn
If Rm Rm
0100 nnnn mmmm 1100 EX EX 1 1 1 1 1 1 1 1
Sh ift A rithmetic D ynamicallyArithmetically shifts the contents of general register Rn. General register Rm
specifies the shift direction and the number of bits to be shifted.
MSB is
added at the upper end.
MSB = 1), the Rm register is
represented as a two's complement. The left shift range is 0 to 31, and the
right shift range, 1 to 32.
Note
On SH4, if there is a load of the shift amount immediately before an SHAD/SHLD
instruction, the latency of the load is increased by 1 cycle.
Operation
void SHAD (int m, int n)
{
int sgn = R[m] & 0x80000000;
if (sgn == 0)
R[n] <<= (R[m] & 0x1F);
else if ((R[m] & 0x1F) == 0)
{
if ((R[n] & 0x80000000) == 0)
R[n] = 0;
else
R[n] = 0xFFFFFFFF;
}
else
R[n] = (long)R[n] >> ((~R[m] & 0x1F) + 1);
PC += 2;
}
shal Rn
T
0100 nnnn 00100000 MSB
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift A rithmetic L eftArithmetically shifts the contents of general register Rn one bit to the left
and stores the result in Rn. The bit shifted out of the operand is transferred
to the T bit.
Operation
void SHAL (int n)
{
if ((R[n] & 0x80000000) == 0)
T = 0;
else
T = 1;
R[n] <<= 1;
PC += 2;
}
Example
shal r0 ! Before execution: r0 = 0x80000001, T = 0
! After execution: r0 = 0x00000002, T = 1
shar Rn
MSB
0100 nnnn 00100001 LSB
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift A rithmetic R ightArithmetically shifts the contents of general register Rn one bit to the right
and stores the result in Rn. The bit shifted out of the operand is transferred
to the T bit.
Operation
void SHAR (int n)
{
long temp;
if ((R[n] & 0x00000001) == 0)
T = 0;
else
T = 1;
if ((R[n] & 0x80000000) == 0)
temp = 0;
else
temp = 1;
R[n] >>= 1;
if (temp == 1)
R[n] |= 0x80000000;
else
R[n] &= 0x7FFFFFFF;
PC += 2;
}
Example
shar r0 ! Before execution: r0 = 0x80000001, T = 0
! After execution: r0 = 0xC0000000, T = 1
shld Rm,Rn
If Rm Rm
0100 nnnn mmmm 1101 EX EX 1 1 1 1 1 1 1 1
Sh ift L ogical D ynamicallyLogically shifts the contents of general register Rn. General register Rm
specifies the shift direction and the number of bits to be shifted.
MSB = 1), the Rm register is
represented as a two's complement. The left shift range is 0 to 31, and the
right shift range, 1 to 32.
Note
On SH4, if there is a load of the shift amount immediately before an SHAD/SHLD
instruction, the latency of the load is increased by 1 cycle.
Operation
void SHLD (int m, int n)
{
int sgn = R[m] & 0x80000000;
if (sgn == 0)
R[n] <<= (R[m] & 0x1F);
else if ((R[m] & 0x1F) == 0)
R[n] = 0;
else
R[n] = (unsigned)R[n] >> ((~R[m] & 0x1F) + 1);
PC += 2;
}
shll Rn
T
0100 nnnn 00000000 MSB
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift L ogical L eftLogically shifts the contents of general register Rn one bit to the left and
stores the result in Rn. The bit shifted out of the operand is transferred to
the T bit.
Note
Effectively, the operation performed is the same as the SHAL instruction.
Operation
void SHLL (int n)
{
if ((R[n] & 0x80000000) == 0)
T = 0;
else
T = 1;
R[n] <<= 1;
PC += 2;
}
Example
shll r0 ! Before execution: r0 = 0x80000001, T = 0
! After execution: r0 = 0x00000002, T = 1
shll2 Rn
Rn
0100 nnnn 00001000 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift L ogical L eft 2 BitsLogically shifts the contents of general register Rn 2 bits to the left and
stores the result in Rn. The bits shifted out of the operand are discarded.
Operation
void SHLL2 (int n)
{
R[n] <<= 2;
PC += 2;
}
Example
shll2 r0 ! Before execution: r0 = 0x12345678
! After execution: r0 = 0x48D159E0
shll8 Rn
Rn
0100 nnnn 00011000 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift L ogical L eft 8 BitsLogically shifts the contents of general register Rn 8 bits to the left and
stores the result in Rn. The bits shifted out of the operand are discarded.
Operation
void SHLL8 (int n)
{
R[n] <<= 8;
PC += 2;
}
Example
shll8 r0 ! Before execution: r0 = 0x12345678
! After execution: r0 = 0x34567800
shll16 Rn
Rn
0100 nnnn 00101000 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift L ogical L eft 16 BitsLogically shifts the contents of general register Rn 16 bits to the left and
stores the result in Rn. The bits shifted out of the operand are discarded.
Operation
void SHLL16 (int n)
{
R[n] <<= 16;
PC += 2;
}
Example
shll16 r0 ! Before execution: r0 = 0x12345678
! After execution: r0 = 0x56780000
shlr Rn
0
0100 nnnn 00000001 LSB
EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift L ogical R ightLogically shifts the contents of general register Rn one bit to the right and
stores the result in Rn. The bit shifted out of the operand is transferred to
the T bit.
Operation
void SHLR (int n)
{
if ((R[n] & 0x00000001) == 0)
T = 0;
else
T = 1;
R[n] >>= 1;
R[n] &= 0x7FFFFFFF;
PC += 2;
}
Example
shlr r0 ! Before execution: r0 = 0x80000001, T = 0
! After execution: r0 = 0x40000000, T = 1
shlr2 Rn
Rn
0100 nnnn 00001001 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift L ogical R ight 2 BitsLogically shifts the contents of general register Rn 2 bits to the right, and
stores the result in Rn. The bits shifted out of the operand are discarded.
Operation
void SHLR2 (int n)
{
R[n] >>= 2;
R[n] &= 0x3FFFFFFF;
PC += 2;
}
Example
shlr2 r0 ! Before execution: r0 = 0x12345678
! After execution: r0 = 0x048D159E
shlr8 Rn
Rn
0100 nnnn 00011001 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift L ogical R ight 8 BitsLogically shifts the contents of general register Rn 8 bits to the right, and
stores the result in Rn. The bits shifted out of the operand are discarded.
Operation
void SHLR8 (int n)
{
R[n] >>= 8;
R[n] &= 0x00FFFFFF;
PC += 2;
}
Example
shlr8 r0 ! Before execution: r0 = 0x12345678
! After execution: r0 = 0x00123456
shlr16 Rn
Rn
0100 nnnn 00101001 EX EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sh ift L ogical R ight 16 BitsLogically shifts the contents of general register Rn 16 bits to the right and
stores the result in Rn. The bits shifted out of the operand are discarded.
Operation
void SHLR16 (int n)
{
R[n] >>= 16;
R[n] &= 0x0000FFFF;
PC += 2;
}
Example
shlr16 r0 ! Before execution: r0 = 0x12345678
! After execution: r0 = 0x00001234
Branch Instructions
bf label
If T
10001011 dddddddd BR BR 1 1 1/3 1/3 1 1 1-3 1/3 1/3 1/3 1/3 1/3 1/2 1
B ranch if F alseThis is a conditional branch instruction that references the T bit. The branch
is taken if T = 0, and not taken if T = 1. The branch destination is address
(PC + 4 + displacement × 2). The PC source value is the BF instruction address.
As the 8-bit displacement is multiplied by two after sign-extension, the branch
destination can be located in the range from -256 to +254 bytes from the BF
instruction.
Note
If the branch destination cannot be reached, the branch must be handled by using
BF in combination with a BRA or JMP instruction, for example.
FPU related hardware bug
which affects this instruction. The recommended workaround is to use bt/s with
a nop in the delay slot.
See also documents "sh2eoc.pdf" and "win_update_a.pdf".
Operation
void BF (int d)
{
int disp;
if ((d & 0x80) == 0)
disp = (0x000000FF & d);
else
disp = (0xFFFFFF00 | d);
if (T == 0)
PC = PC + 4 + (disp << 1);
else
PC += 2;
}
Example
clrt ! T is always cleared to 0
bt TARGET_T ! Does not branch, because T = 0
bf TARGET_F ! Branches to TARGET_F, because T = 0
nop
nop ! ← The PC location is used to calculate the branch destination address of the BF instruction
TARGET_F: ! ← Branch destination of the BF instruction
Possible Exceptions
Slot illegal instruction exception
bf/s label
If T
10001111 dddddddd BR BR 1 1/2 1/2 1 1 1-3 1/2 1/2 1/2 1/2 1/2 1
This is a delayed conditional branch instruction that references the T bit.
If T = 1, the next instruction is executed and the branch is not taken.
If T = 0, the branch is taken after execution of the next instruction.
PC + 4 + displacement × 2). The PC source
value is the BF/S instruction address. As the 8-bit displacement is multiplied
by two after sign-extension, the branch destination can be located in the range
from -256 to +254 bytes from the BF/S instruction.
Note
As this is a delayed branch instruction, when the branch condition is satisfied,
the instruction following this instruction is executed before the branch
destination instruction.
S in combination with a BRA or JMP instruction, for example.
Operation
void BFS (int d)
{
int disp;
unsigned int temp;
temp = PC;
if ((d & 0x80) == 0)
disp = (0x000000FF & d);
else
disp = (0xFFFFFF00 | d);
if (T == 0)
PC = PC + 4 + (disp << 1);
else
PC += 4;
Delay_Slot (temp + 2);
}
Example
clrt ! T is always 0
bt/s TARGET_T ! Does not branch, because T = 0
nop
bf/s TARGET_F ! Branches to TARGET_F, because T = 0
add r0,r1 ! Executed before branch .
nop ! ← The PC location is used to calculate the branch destination address of the BF/S instruction
TARGET_F: ! ← Branch destination of the BF/S instruction
Possible Exceptions
Slot illegal instruction exception
bt label
If T
10001001 dddddddd BR BR 1 1 1/3 1/3 1 1 1-3 1/3 1/3 1/3 1/3 1/3 1/2 1
B ranch if T rueThis is a conditional branch instruction that references the T bit. The branch
is taken if T = 1, and not taken if T = 0. The branch destination is address
(PC + 4 + displacement × 2). The PC source value is the BT instruction address.
As the 8-bit displacement is multiplied by two after sign-extension, the branch
destination can be located in the range from -256 to +254 bytes from the BT
instruction.
Note
If the branch destination cannot be reached, the branch must be handled by using
BT in combination with a BRA or JMP instruction, for example.
FPU related hardware bug
which affects this instruction. The recommended workaround is to use bt/s with
a nop in the delay slot.
See also documents "sh2eoc.pdf" and "win_update_a.pdf".
Operation
void BT (int d)
{
int disp;
if ((d & 0x80) == 0)
disp = (0x000000FF & d);
else
disp = (0xFFFFFF00 | d);
if (T == 1)
PC = PC + 4 + (disp << 1);
else
PC += 2;
}
Example
sett ! T is always 1
bf TARGET_F ! Does not branch, because T = 1
bt TARGET_T ! Branches to TARGET_T, because T = 1
nop
nop ! ← The PC location is used to calculate the branch destination address of the BT instruction
TARGET_T: ! ← Branch destination of the BT instruction
Possible Exceptions
Slot illegal instruction exception
bt/s label
If T
10001101 dddddddd BR BR 1 1/2 1/2 1 1 1-3 1/2 1/2 1/2 1/2 1/2 1
This is a conditional branch instruction that references the T bit. The branch
is taken if T = 1, and not taken if T = 0. The PC source value is the BT/S
instruction address. As the 8-bit displacement is multiplied by two after
sign-extension, the branch destination can be located in the range from -256 to
+254 bytes from the BT/S instruction.
Note
As this is a delayed branch instruction, when the branch condition is satisfied,
the instruction following this instruction is executed before the branch
destination instruction.
S in combination with a BRA or JMP instruction, for example.
Operation
void BTS (int d)
{
int disp;
unsigned temp;
temp = PC;
if ((d & 0x80) == 0)
disp = (0x000000FF & d);
else
disp = (0xFFFFFF00 | d);
if (T == 1)
PC = PC + 4 + (disp << 1);
else
PC += 4;
Delay_Slot (temp + 2);
}
Example
sett ! T is always 1
bf/s TARGET_F ! Does not branch, because T = 1
nop
bt/s TARGET_T ! Branches to TARGET, because T = 1
add r0,r1 ! Executes before branching.
nop ! ← The PC location is used to calculate the branch destination address of the BT/S instruction
TARGET_T: ! ← Branch destination of the BT/S instruction
Possible Exceptions
Slot illegal instruction exception
bra label
disp
1010 dddddddddddd BR BR 1 1 2 2 1 1 1-3 2 2 2 2 2 2 1
Bra nchThis is an unconditional branch instruction. The branch destination is address
(PC + 4 + displacement × 2). The PC source value is the BRA instruction address.
As the 12-bit displacement is multiplied by two after sign-extension, the branch
destination can be located in the range from -4096 to +4094 bytes from the BRA
instruction. If the branch destination cannot be reached, this branch can be
performed with a JMP instruction.
Note
As this is a delayed branch instruction, the instruction following this
instruction is executed before the branch destination instruction.
Operation
void BRA (int d)
{
int disp;
unsigned int temp;
temp = PC;
if ((d & 0x800) == 0)
disp = (0x00000FFF & d);
else
disp = (0xFFFFF000 | d);
PC = PC + 4 + (disp << 1);
Delay_Slot(temp + 2);
}
Example
bra TARGET ! Branches to TARGET
add r0,r1 ! Executes ADD before branching
nop ! ← The PC location is used to calculate the branch destination address of the BRA instruction
TARGET: ! ← Branch destination of the BRA instruction
Possible Exceptions
Slot illegal instruction exception
braf Rm
Rm
0000 mmmm 00100011 CO BR 1 2 2 1 2 4 2 2 2 2 3 1
Bra nch F arThis is an unconditional branch instruction. The branch destination is address
(PC + 4 + Rm).
Note
As this is a delayed branch instruction, the instruction following this
instruction is executed before the branch destination instruction.
Operation
void BRAF (int m)
{
unsigned int temp;
temp = PC;
PC = PC + 4 + R[m];
Delay_Slot (temp + 2);
}
Example
mov.l #(TARGET-BSRF_PC),r0 ! Sets displacement.
bra TARGET ! Branches to TARGET
add r0,r1 ! Executes ADD before branching
BRAF_PC: ! ← The PC location is used to calculate the
! branch destination address of the BRAF instruction
nop
TARGET: ! ← Branch destination of the BRAF instruction
Possible Exceptions
Slot illegal instruction exception
bsr label
PC
1011 dddddddddddd BR BR 1 1 2 2 1 1 1-3 2 2 2 2 2 2 1
B ranch to S ubr outineBranches to address (PC + 4 + displacement × 2), and stores address (PC + 4) in
PR . The PC source value is the BSR instruction address.
As the 12-bit displacement is multiplied by two after sign-extension, the branch
destination can be located in the range from -4096 to +4094 bytes from the BSR
instruction. If the branch destination cannot be reached, this branch can be
performed with a JSR instruction.
Note
As this is a delayed branch instruction, the instruction following this
instruction is executed before the branch destination instruction.
Operation
void BSR (int d)
{
int disp;
unsigned int temp;
temp = PC;
if ((d & 0x800) == 0)
disp = (0x00000FFF & d);
else
disp = (0xFFFFF000 | d);
PR = PC + 4;
PC = PC + 4 + (disp << 1);
Delay_Slot (temp + 2);
}
Example
bsr TARGET ! Branches to TARGET
mov r3,r4 ! Executes the MOV instruction before branching
add r0,r1 ! ← The PC location is used to calculate the branch destination
! address of the BSR instruction (return address for when the
! subroutine procedure is completed (PR data))
TARGET: ! ← Procedure entrance
mov r2,r3
rts ! Returns to the above ADD instruction
mov #1,r0 ! Executes MOV before branching
Possible Exceptions
Slot illegal instruction exception
bsrf Rm
PC
0000 mmmm 00000011 CO BR 1 2 2 1 2 4 2 2 2 2 3 1
B ranch to S ubr outine F arBranches to address (PC + 4 + Rm), and stores address (PC + 4) in PR . The PC
source value is the BSRF instruction address. The branch destination address is
the result of adding the 32-bit contents of general register Rm to PC + 4.
Note
As this is a delayed branch instruction, the instruction following this
instruction is executed before the branch destination instruction.
Operation
void BSRF (int m)
{
unsigned int temp;
temp = PC;
PR = PC + 4;
PC = PC + 4 + R[m];
Delay_Slot (temp + 2);
}
Example
mov.l #(TARGET-BSRF_PC),r0 ! Sets displacement.
brsf r0 ! Branches to TARGET
mov r3,r4 ! Executes the MOV instruction before
branching
BSRF_PC: ! ← The PC location is used to calculate the branch destination with BSRF.
add r0,r1
TARGET: ! ←Procedure entrance
mov r2,r3
rts ! Returns to the above ADD instruction
mov #1,r0 ! Executes MOV before branching
Possible Exceptions
Slot illegal instruction exception
jmp @Rm
Rm
0100 mmmm 00101011 CO BR 1 1 2 2 1 2 4 2 2 2 2 2 3 1
J ump Unconditionally makes a delayed branch to the address specified by Rm.
Note
As this is a delayed branch instruction, the instruction following this
instruction is executed before the branch destination instruction.
Operation
void JMP (int m)
{
unsigned int temp;
temp = PC;
PC = R[m];
Delay_Slot (temp + 2);
}
Example
mov.l JMP_TABLE,r0 ! Address of r0 = TARGET
jmp @r0 ! Branches to TARGET
mov r0,r1 ! Executes MOV before branching
.align 4
JMP_TABLE: .data.l TARGET ! Jump table
TARGET: add #1,r1 ! ← Branch destination
Possible Exceptions
Slot illegal instruction exception
jsr @Rm
PC
0100 mmmm 00001011 CO BR 1 1 2 2 1 2 4 2 2 2 2 2 3 1
J ump to S ubr outineMakes a delayed branch to the subroutine procedure at the specified address
after execution of the following instruction. Return address (PC + 4) is saved
in PR , and a branch is made to the address indicated by general register Rm.
JSR is used in combination with RTS for subroutine procedure calls.
Note
As this is a delayed branch instruction, the instruction following this
instruction is executed before the branch destination instruction.
Operation
void JSR (int m)
{
unsigned int temp;
temp = PC;
PR = PC + 4;
PC = R[m];
Delay_Slot (temp + 2);
}
Example
mov.l JSR_TABLE,r0 ! Address of r0 = TARGET
jsr @r0 ! Branches to TARGET
xor r1,r1 ! Executes XOR before branching
add r0,r1 ! ← Return address for when the subroutine procedure is completed (PR data)
.align 4
JSR_TABLE: .data.l TARGET ! Jump table
TARGET: nop ! ← Procedure entrance
mov r2,r3
rts ! Returns to the above ADD instruction
mov #70,r1 ! Executes MOV before RTS
Possible Exceptions
Slot illegal instruction exception
jsr/n @Rm
PC
0100 mmmm 01001011 3 3
J ump to S ubr outine with N o Delay SlotBranches to a subroutine procedure at the designated address. The contents of
PC are stored in PR and execution branches to the address indicated by the
contents of general register Rm as 32-bit data. The stored contents of PC
indicate the starting address of the second instruction after the present
instruction. This instruction is used with RTS as a subroutine procedure call.
Note
This is not a delayed branch instruction.
Operation
void JSRN (int m)
{
unsigned long temp;
temp = PC;
PR = PC + 2;
PC = R[m];
}
Possible Exceptions
Slot illegal instruction exception
jsr/n @@(disp8,TBR)
PC
10000011 dddddddd 5 5
J ump to S ubr outine with N o Delay SlotBranches to a subroutine procedure at the designated address. The contents of PC
are stored in PR and execution branches to the address indicated by the address
read from memory address (disp × 4 + TBR). The stored contents of PC indicate
the starting address of the second instruction after the present instruction.
This instruction is used with RTS as a subroutine procedure call.
Note
This is not a delayed branch instruction.
Operation
void JSRNM (int d)
{
long disp = (0x000000FF & d);
PR = PC + 2;
PC = Read_32 (TBR + (disp << 2));
}
Possible Exceptions
Slot illegal instruction exception
rts
PR
0000000000001011 CO BR 1 1 2 2 1 2 1-4 2 2 2 2 2 3 1
R et urn from S ubroutineReturns from a subroutine procedure by restoring the PC from PR . Processing
continues from the address indicated by the restored PC value. This instruction
can be used to return from a subroutine procedure called by a BSR or JSR
instruction to the source of the call.
Note
As this is a delayed branch instruction, the instruction following this
instruction is executed before the branch destination instruction.
PR must be executed before the RTS instruction.
This restore instruction cannot be in the RTS delay slot.
Operation
void RTS (void)
{
unsigned int temp;
temp = PC;
PC = PR;
Delay_Slot (temp + 2);
}
Example
mov.l TABLE,r3 ! r3 = Address of TARGET
jsr @r3 ! Branches to TARGET
nop ! Executes NOP before branching
add r0,r1 ! ← Return address for when the subroutine procedure is completed (PR data)
TABLE: .data.l TARGET ! Jump table
TARGET: mov r1,r0 ! ← Procedure entrance
rts ! PR data → PC
mov #12,r0 ! Executes MOV before branching
Possible Exceptions
Slot illegal instruction exception
rts/n
PR
0000000001101011 3 3
R et urn from S ubroutine with N o Delay SlotPerforms a return from a subroutine procedure. That is, the PC is restored from
PR , and processing is resumed from the address indicated by the PC . This
instruction enables a return to be made from a subroutine procedure called by a
BSR or JSR instruction to the origin of the call.
Note
This is not a delayed branch instruction.
Operation
void RTSN (void)
{
PC = PR;
}
Possible Exceptions
Slot illegal instruction exception
rtv/n Rm
Rm
0000 mmmm 01111011 3 3
R et urn to V alue and from Subroutine with N o Delay SlotPerforms a return from a subroutine procedure after a transfer from specified
general register Rm to R0. That is, after the Rm value is stored in R0, the PC
is restored from PR , and processing is resumed from the address indicated by the
PC . This instruction enables a return to be made from a subroutine procedure
called by a BSR or JSR instruction to the origin of the call.
Note
This is not a delayed branch instruction.
Operation
void RTVN (int m)
{
R[0] = R[m];
PC = PR;
}
Possible Exceptions
Slot illegal instruction exception
System Control Instructions
clrmac
0
0000000000101000 CO EX 1 1 1 1 1 1 1 1 1 1 1 1 3 1
Cl ear MAC RegisterClears the MACH and MACL registers.
Operation
void CLRMAC (void)
{
MACH = 0;
MACL = 0;
PC += 2;
}
Example
clrmac ! Clears and initializes the MAC register
mac.w @r0+,@r1+ ! Multiply and accumulate operation
mac.w @r0+,@r1+
clrs
0
0000000001001000 0
CO EX 1 1 1 1 1 1
Cl ear S BitClears the S bit to 0.
Operation
void CLRS (void)
{
S = 0;
PC += 2;
}
clrt
0
0000000000001000 0
MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Cl ear T BitClears the T bit.
Operation
void CLRT (void)
{
T = 0;
PC += 2;
}
Example
clrt ! Before execution: T = 1
! After execution: T = 0
icbi @Rn
Invalidate instruction cache block indicated by logical address
0000 nnnn 11100011 CO 16 13
I nstruction C ache B lock I nvalidateAccesses the instruction cache at the effective address indicated by the
contents of Rn. When the cache is hit, the corresponding cache block is
invalidated (the V bit is cleared to 0). At this time, write-back is not
performed. No operation is performed in the case of a cache miss or access to
a non-cache area.
Note
When a program is overwriting RAM to modify its own execution, the corresponding
block of the instruction cache should be invalidated by the ICBI instruction.
This prevents execution of the program from the instruction cache, where the
non-overwritten instructions are stored.
Operation
void ICBI (int n)
{
invalidate_instruction_cache_block (R[n]);
PC += 2;
}
Possible Exceptions
Instruction TLB multiple-hit exception
Instruction TLB miss exception
Instruction TLB protection violation exception
Instruction address error
Slot illegal instruction exception
Exceptions may occur when invalidation is not performed.
ldbank @Rm,R0
(Specified register bank entry)
0100 mmmm 11100101 6 5
L oad register Bank The register bank entry indicated by the contents of general register Rm is
transferred to general register R0. The register bank number and register stored
in the bank are specified by general register Rm.
Note
The architecture supports a maximum of 512 banks. However, the number of banks
differs depending on the product.
Operation
void LDBANK (int m)
{
R[0] = Read_Bank_32 (R[m]);
PC += 2;
}
ldc Rm,SR
Rm
0100 mmmm 00001110 LSB
CO CO 1 1 3 3 1 4 7 1 1 2 2 5 4 4
L oad to C ontrol RegisterStores the source operand in the control register SR .
Note
This instruction is only usable in privileged mode. Issuing this instruction in
user mode will cause an illegal instruction exception.
Operation
void LDCSR (int m)
{
#if SH1 || SH2 || SH2 || SH3
SR = R[m] & 0x0FFF0FFF;
#elif SH2A
SR = R[m] & 0x000063F3;
#elif SH4 || SH4A
SR = R[m] & 0x700083F3;
#endif
PC += 2;
}
Example
ldc r0,SR ! Before execution: r0 = 0xFFFFFFFF, SR = 0x00000000
! After execution: SR = 0x0FFF0FFF
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
ldc.l @Rm+,SR
(Rm)
0100 mmmm 00000111 LSB
CO CO 1 1 5 5 2 4 9 3 3 4 4 7 4/4 4
L oad to C ontrol RegisterStores the source operand in the control register SR .
Note
This instruction is only usable in privileged mode. Issuing this instruction in
user mode will cause an illegal instruction exception.
Operation
void LDCMSR (int m)
{
#if SH1 || SH2 || SH2 || SH3
SR = Read_32 (R[m]) & 0x0FFF0FFF;
#elif SH2A
SR = Read_32 (R[m]) & 0x000063F3;
#elif SH4 || SH4A
SR = Read_32 (R[m]) & 0x700083F3;
#endif
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
ldc Rm,TBR
Rm
0100 mmmm 01001010 1 1
L oad to C ontrol RegisterStores a source operand in control register TBR.
Operation
void LDCTBR (int m)
{
TBR = R[m];
PC += 2;
}
ldc Rm,GBR
Rm
0100 mmmm 00011110 CO LS 1 1 1 1 1 3 1 1 1 1 1 1/3 3 1
L oad to C ontrol RegisterStores a source operand in control register GBR .
Note
This instruction can also be issued in user mode.
Operation
void LDCGBR (int m)
{
GBR = R[m];
PC += 2;
}
ldc.l @Rm+,GBR
(Rm)
0100 mmmm 00010111 CO LS 1 1 1 1 1 3 1 3 3 2 2 1/5 3/3 1
L oad to C ontrol RegisterStores a source operand in control register GBR .
Note
This instruction can also be issued in user mode.
Operation
void LDCMGBR (int m)
{
GBR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Example
ldc.l @r15+,GBR ! Before execution: r15 = 0x10000000
! After execution: r15 = 0x10000004, GBR = @0x10000000
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
ldc Rm,VBR
Rm
0100 mmmm 00101110 CO LS 1 1 1 1 1 1 1 1 1 1 1 1/3 3 1
Stores a source operand in control register VBR .
Operation
void LDCVBR (int m)
{
VBR = R[m];
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
ldc.l @Rm+,VBR
(Rm)
0100 mmmm 00100111 CO LS 1 1 1 1 1 1 1 3 3 2 2 1/5 1/3 1
Stores a source operand in control register VBR .
Operation
void LDCMVBR (int m)
{
VBR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
ldc Rm,MOD
Rm
0100 mmmm 01011110 1 1/3
L oad to C ontrol RegisterStores a source operand in control register MOD.
Note
On the SH-DSP the latency of this instruction is 1 cycle.
Operation
void LDCMOD (int m)
{
MOD = R[m];
PC += 2;
}
ldc.l @Rm+,MOD
(Rm)
0100 mmmm 01010111 1 1/5
L oad to C ontrol RegisterStores a source operand in control register MOD.
Note
On the SH-DSP the latency of this instruction is 3 cycles.
Operation
void LDCMMOD (int m)
{
MOD = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
ldc Rm,RE
Rm
0100 mmmm 01111110 1 1/3
L oad to C ontrol RegisterStores a source operand in control register RE.
Note
On the SH-DSP the latency of this instruction is 1 cycle.
Operation
void LDCRE (int m)
{
RE = R[m];
PC += 2;
}
ldc.l @Rm+,RE
(Rm)
0100 mmmm 01110111 1 1/5
L oad to C ontrol RegisterStores a source operand in control register RE.
Note
On the SH-DSP the latency of this instruction is 3 cycles.
Operation
void LDCMRE (int m)
{
RE = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
ldc Rm,RS
Rm
0100 mmmm 01101110 1 1/3
L oad to C ontrol RegisterStores a source operand in control register RS.
Note
On the SH-DSP the latency of this instruction is 1 cycle.
Operation
void LDCRS (int m)
{
RS = R[m];
PC += 2;
}
ldc.l @Rm+,RS
(Rm)
0100 mmmm 01100111 1 1/5
L oad to C ontrol RegisterStores a source operand in control register RS.
Note
On the SH-DSP the latency of this instruction is 3 cycles.
Operation
void LDCMRS (int m)
{
RS = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
ldc Rm,SGR
Rm
0100 mmmm 00111010 CO 4 4
Stores a source operand in control register SGR.
Note
Not sure whether it is also available on SH4.
It is not marked as new instruction for SH4A but is also not listed in SH4
manuals.
Operation
void LDCSGR (int m)
{
SGR = R[m];
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
ldc.l @Rm+,SGR
(Rm)
0100 mmmm 00110110 CO 4 4
Stores a source operand in control register SGR.
Note
Not sure whether it is also available on SH4.
It is not marked as new instruction for SH4A but is also not listed in SH4
manuals.
Operation
void LDCMSGR (int m)
{
SGR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
ldc Rm,SSR
Rm
0100 mmmm 00111110 CO LS 1 1 1 1/3 3 1
Stores a source operand in control register SSR.
Operation
void LDCSSR (int m)
{
SSR = R[m],
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
ldc.l @Rm+,SSR
(Rm)
0100 mmmm 00110111 CO LS 1 1 1 1/5 1/3 1
Stores a source operand in control register SSR.
Operation
void LDCMSSR (int m)
{
SSR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
ldc Rm,SPC
Rm
0100 mmmm 01001110 CO LS 1 3 1 1/3 1 1
Stores a source operand in control register SPC.
Operation
void LDCSPC (int m)
{
SPC = R[m];
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
ldc.l @Rm+,SPC
(Rm)
0100 mmmm 01000111 CO LS 1 1 1 1/5 1/3 1
Stores a source operand in control register SPC.
Operation
void LDCMSPC (int m)
{
SPC = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
ldc Rm,DBR
Rm
0100 mmmm 11111010 CO CO 1 4 3 4
Stores a source operand in control register DBR.
Operation
void LDCDBR (int m)
{
DBR = R[m];
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
ldc.l @Rm+,DBR
(Rm)
0100 mmmm 11110110 CO CO 1 4 1/3 4
Stores a source operand in control register DBR.
Operation
void LDCMDBR (int m)
{
DBR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
ldc Rm,Rn_BANK
Rm
0100 mmmm 1 nnn 1110 CO LS 1 1 1 1/3 3 1
Stores a source operand in banked general register.
Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is
accessed when this bit is 0.
Operation
void LDCRn_BANK (int m)
{
Rn_BANK = R[m];
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
ldc.l @Rm+,Rn_BANK
(Rm)
0100 mmmm 1 nnn 0111 CO LS 1 1 1 1/5 1/3 1
Stores a source operand in banked general register.
Rn_BANK0 is accessed when the RB bit in the SR register is 1, and Rn_BANK1 is
accessed when this bit is 0.
Operation
void LDCMRn_BANK (int m)
{
Rn_BANK = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
ldre @(disp,PC)
disp
10001110 dddddddd 1 3
L oad Effective Address to RE RegisterStores the effective address of the source operand in the repeat end register
RE. The effective address is an address specified by PC + displacement. The PC
is the address four bytes after this instruction. The 8-bit displacement is
sign-extended and doubled. Consequently, the relative interval from the branch
destination is -256 to +254 bytes.
Note
The effective address value designated for the RE reregister is different from
the actual repeat end address. Refer to RS and RE Design Rules, for more
information.
PC becomes the "first address +2" of the branch destination.
DSP the latency of this instruction is 1 cycle.
Operation
void LDRE (int d)
{
long disp;
if ((d & 0x80) == 0)
disp = (0x000000FF & (long)d);
else
disp = (0xFFFFFF00 | (long)d);
RE = PC + (disp << 1);
PC += 2;
}
Example
ldrs start ! Set repeat start address to RS
ldre end ! Set repeat end address to RE
setrc #32 ! Repeat 32 times from <instruction A> to <instruction B>
...
start:
<instruction A>
...
...
...
end:
<instruction B>
...
ldrs @(disp,PC)
disp
10001100 dddddddd 1 3
L oad Effective Address to RS RegisterStores the effective address of the source operand in the repeat start register
RS. The effective address is an address specified by PC + displacement. The PC
is the address four bytes after this instruction. The 8-bit displacement is
sign-extended and doubled. Consequently, the relative interval from the branch
destination is -256 to +254 bytes.
Note
When the instructions of the repeat (loop) program are below 3, the effective
address value designated for the RS register is different from the actual repeat
start address. Refer to "RS and RE setting rule", for more information. If this
PC
becomes "the first address +2" of the branch destination.
DSP the latency of this instruction is 1 cycle.
Operation
void LDRS (int d)
{
long disp;
if ((d & 0x80) == 0)
disp = (0x000000FF & (long)d);
else
disp = (0xFFFFFF00 | (long)d);
RS = PC + (disp << 1);
PC += 2;
}
Example
ldrs start ! Set repeat start address to RS
ldre end ! Set repeat end address to RE
setrc #32 ! Repeat 32 times from <instruction A> to <instruction B>
...
start:
<instruction A>
...
...
...
end:
<instruction B>
...
lds Rm,MACH
Rm
0100 mmmm 00001010 CO LS 1 1 1 1 1 1 1 1 1 1 1 1 3 1
L oad to FPU S ystem registerStores the source operand into the system register MACH .
Note
On SH1, only the lower 10 bits are stored in MACH .
MAC * is followed by an STS.L MAC *,@-Rn instruction, the
latency of the LDS to MAC * is 4 cycles. When an LDS to MAC * is followed by
MAC .W/MAC .L, the latency of the LDS to MAC * is 1 cycle.
Operation
void LDSMACH (int m)
{
MACH = R[m];
#if SH1
if ((MACH & 0x00000200) == 0)
MACH &= 0x000003FF;
else
MACH |= 0xFFFFFC00;
#endif
PC += 2;
}
lds.l @Rm+,MACH
(Rm)
0100 mmmm 00000110 CO LS 1 1 1 1 1 1 1 1 1 2 2 1 1/3 1
L oad to FPU S ystem registerStores the source operand into the system register MACH .
Note
On SH4, when an LDS to MAC * is followed by an STS.L MAC *,@-Rn instruction, the
latency of the LDS to MAC * is 4 cycles. When an LDS to MAC * is followed by
MAC .W/MAC .L, the latency of the LDS to MAC * is 1 cycle.
Operation
void LDSMMACH (int m)
{
MACH = Read_32 (R[m]);
#if SH1
if ((MACH & 0x00000200) == 0)
MACH &= 0x000003FF;
else
MACH |= 0xFFFFFC00;
#endif
R[m] += 4;
PC += 2;
}
Example
lds.l @r15+,MACL ! Before execution: r15 = 0x10000000
! After execution: r15 = 0x10000004, MACL = @0x1000000
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
lds Rm,MACL
Rm
0100 mmmm 00011010 CO LS 1 1 1 1 1 1 1 1 1 1 1 1 3 1
L oad to FPU S ystem registerStores the source operand into the system register MACL .
Note
On SH4, when an LDS to MAC * is followed by an STS.L MAC *,@-Rn instruction, the
latency of the LDS to MAC * is 4 cycles. When an LDS to MAC * is followed by
MAC .W/MAC .L, the latency of the LDS to MAC * is 1 cycle.
Operation
void LDSMACL (int m)
{
MACL = R[m];
PC += 2;
}
lds.l @Rm+,MACL
(Rm)
0100 mmmm 00010110 CO LS 1 1 1 1 1 1 1 1 1 2 2 1 1/3 1
L oad to FPU S ystem registerStores the source operand into the system register MACL .
Note
On SH4, when an LDS to MAC * is followed by an STS.L MAC *,@-Rn instruction, the
latency of the LDS to MAC * is 4 cycles. When an LDS to MAC * is followed by
MAC .W/MAC .L, the latency of the LDS to MAC * is 1 cycle.
Operation
void LDSMMACL (int m)
{
MACL = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Example
lds.l @r15+,MACL ! Before execution: r15 = 0x10000000
! After execution: r15 = 0x10000004, MACL = @0x10000000
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
lds Rm,PR
Rm
0100 mmmm 00101010 CO LS 1 1 1 1 1 2 1 1 1 1 1 1 3 1
L oad to FPU S ystem registerStores the source operand into the system register PR .
Operation
void LDSPR (int m)
{
PR = R[m];
PC += 2;
}
Example
lds r0,PR ! Before execution: r0 = 0x12345678, PR = 0x00000000
! After execution: PR = 0x12345678
lds.l @Rm+,PR
(Rm)
0100 mmmm 00100110 CO LS 1 1 1 1 1 2 1 1 1 2 2 1 2/3 1
L oad to FPU S ystem registerStores the source operand into the system register PR .
Operation
void LDSMPR (int m)
{
PR = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
lds Rm,DSR
Rm
0100 mmmm 01101010 1 1
L oad to FPU S ystem RegisterStores the source operand into the DSP register DSR .
Operation
void LDSDSR (int m)
{
DSR = R[m] & 0x0000000F;
PC += 2;
}
lds Rm,A0
Rm
0100 mmmm 01111010 1 1
L oad to FPU S ystem registerStores the source operand into the DSP register A0.
Operation
void LDSA0 (long m)
{
A0 = R[m];
if ((A0 & 0x80000000) == 0)
A0G = 0x00;
else
A0G = 0xFF;
PC += 2;
}
lds.l @Rm+,DSR
(Rm)
0100 mmmm 01100110 1 1/5
L oad to FPU S ystem RegisterStores the source operand into the DSP register DSR .
Note
On the SH-DSP the latency of this instruction is 1 cycle.
Operation
void LDSMDSR (int m)
{
DSR = Read_32 (R[m]) & 0x0000000F;
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
lds.l @Rm+,A0
(Rm)
0100 mmmm 01110110 1 1
L oad to FPU S ystem registerStores the source operand into the DSP register A0. The MSB of the data is
copied into A0G.
Operation
void LDSMA0 (int m)
{
A0 = Read_32 (R[m]);
if ((A0 & 0x80000000) == 0)
A0G = 0x00;
else
A0G = 0xFF;
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
lds Rm,X0
Rm
0100 mmmm 10001010 1 1
L oad to FPU S ystem registerStores the source operand into the DSP register X0.
Operation
void LDSX0 (int m)
{
X0 = R[m];
PC += 2;
}
lds.l @Rm+,X0
(Rm)
0100 nnnn 10000110 1 1/5
L oad to FPU S ystem registerStores the source operand into the DSP register X0.
Operation
void LDSMX0 (int m)
{
X0 = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
lds Rm,X1
Rm
0100 mmmm 10011010 1 1
L oad to FPU S ystem registerStores the source operand into the DSP register X1.
Operation
void LDSX1 (int m)
{
X1 = R[m];
PC += 2;
}
lds.l @Rm+,X1
(Rm)
0100 nnnn 10010110 1 1/5
L oad to FPU S ystem registerStores the source operand into the DSP register X1.
Operation
void LDSMX1 (int m)
{
X1 = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
lds Rm,Y0
Rm
0100 mmmm 10101010 1 1
L oad to FPU S ystem registerStores the source operand into the DSP register Y0.
Operation
void LDSY0 (int m)
{
Y0 = R[m];
PC += 2;
}
lds.l @Rm+,Y0
(Rm)
0100 nnnn 10100110 1 1/5
L oad to FPU S ystem registerStores the source operand into the DSP register Y0.
Operation
void LDSMY0 (int m)
{
Y0 = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
lds Rm,Y1
Rm
0100 mmmm 10111010 1 1
L oad to FPU S ystem registerStores the source operand into the DSP register Y1.
Operation
void LDSY1 (int m)
{
Y1 = R[m];
PC += 2;
}
lds.l @Rm+,Y1
(Rm)
0100 nnnn 10110110 1 1
L oad to FPU S ystem registerStores the source operand into the DSP register Y1.
Operation
void LDSMY1 (int m)
{
Y1 = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data address error
ldtlb
PTEH
0000000000111000 CO CO 1 1 1 1 1 1
L oad PTEH/PTEL to TLB Loads the contents of the PTEH /PTEL registers into the TLB (translation
lookaside buffer) specified by MMUCR .URC (random counter field in the MMC
control register).
Note
As this instruction loads the contents of the PTEH /PTEL registers into a TLB , it
should be used either with the MMU disabled, or in the P1 or P2 virtual space
with the MMU enabled (see the MMU section of the applicable hardware manual for
details).
Operation
void LDTLB (void)
{
#if SH3
TLB_tag = PTEH;
TLB_data = PTEL;
#elif SH4
TLB[MMUCR.URC].ASID = PTEH & 0x000000FF;
TLB[MMUCR.URC].VPN = (PTEH & 0xFFFFFC00) >> 10;
TLB[MMUCR.URC].PPN = (PTEH & 0x1FFFFC00) >> 10;
TLB[MMUCR.URC].SZ = (PTEL & 0x00000080) >> 6 | (PTEL & 0x00000010) >> 4;
TLB[MMUCR.URC].SH = (PTEH & 0x00000002) >> 1;
TLB[MMUCR.URC].PR = (PTEH & 0x00000060) >> 5;
TLB[MMUCR.URC].WT = (PTEH & 0x00000001);
TLB[MMUCR.URC].C = (PTEH & 0x00000008) >> 3;
TLB[MMUCR.URC].D = (PTEH & 0x00000004) >> 2;
TLB[MMUCR.URC].V = (PTEH & 0x00000100) >> 8;
#endif
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
movca.l R0,@Rn
R0
0000 nnnn 11000011 LS LS 1 1 3-7 1
Mov e with C ache Block A llocationStores the contents of general register R0 in the memory location indicated by
effective address Rn. This instruction differs from other store instructions as
follows.
Operation
void MOVCAL (int n)
{
if (is_write_back_memory (R[n]) && look_up_in_operand_cache (R[n]) == MISS)
allocate_operand_cache_block (R[n]);
Write_32 (R[n], R[0]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
nop
No operation
0000000000001001 MT MT 1 1 1 1 1 1 1 1 1 0 0 1 0 1
Note
Increments the program counter (PC ), advancing the processing flow to execution
of the next instruction.
Operation
void NOP (void)
{
PC += 2;
}
Example
nop ! Executes in one cycle
ocbi @Rn
Invalidate operand cache block
0000 nnnn 10010011 LS LS 1 1 1-2 1
O perand C ache B lock I nvalidateAccesses data using the contents indicated by effective address Rn. In the case
of a hit in the cache, the corresponding cache block is invalidated (the V bit
is cleared to 0). If there is unwritten information (U bit = 1), write-back is
not performed even if write-back mode is selected. No operation is performed in
the case of a cache miss or an access to a non-cache area.
Operation
void OCBI (int n)
{
invalidate_operand_cache_block (R[n]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
Note that the above exceptions are generated even if OCBI does not operate.
ocbp @Rn
Write back and invalidate operand cache block
0000 nnnn 10100011 LS LS 1 1 1-5 1
O perand C ache B lock P urgeAccesses data using the contents indicated by effective address Rn. If the cache
is hit and there is unwritten information (U bit = 1), the corresponding cache
block is written back to external memory and that block is invalidated (the V
bit is cleared to 0). If there is no unwritten information (U bit = 0), the
block is simply invalidated. No operation is performed in the case of a cache
miss or an access to a non-cache area.
Operation
void OCBP (int n)
{
if (is_dirty_block (R[n]))
write_back (R[n])
invalidate_operand_cache_block (R[n]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Note that the above exceptions are generated even if OCBP does not operate.
ocbwb @Rn
Write back operand cache block
0000 nnnn 10110011 LS LS 1 1 1-5 1
O perand C ache B lock W rite B ackAccesses data using the contents indicated by effective address Rn. If the cache
is hit and there is unwritten information (U bit = 1), the corresponding cache
block is written back to external memory and that block is cleaned (the U bit
is cleared to 0). In other cases (i.e. in the case of a cache miss or an access
to a non-cache area, or if the block is already clean), no operation is
performed.
Operation
void OCBWB (int n)
{
if (is_dirty_block (R[n]))
write_back (R[n]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Note that the above exceptions are generated even if OCBWB does not operate.
pref @Rn
(Rn)
0000 nnnn 10000011 LS LS 1 1 1 1 0 1/2 1 1
Pref etch Data to CacheSH4 and SH4A
Note
On products with no cache, this instruction is handled as a NOP instruction.
Operation
void PREF (int n)
{
prefetch_operand_cache_block (R[n]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
prefi @Rn
Reads 32
0000 nnnn 11010011 CO 13 10
Pref etch I nstruction Cache BlockReads a 32-byte block of data starting at a 32-byte boundary within the
instruction cache. The lower 5 bits of the address specified by Rn are masked
by zeroes.
MMU exceptions. In the
event of an error, the PREFI instruction is treated as an NOP (no operation)
instruction.
UTLB or is protected, the
PREFI instruction is treated as an NOP instruction and a TLB exception does not
occur.
Note
This instruction can be used before the SLEEP command is issued to prefetch
instructions for execution on return from the SLEEP state.
Operation
void PREFI (int n)
{
prefetch_instruction_cache_block (R[n]);
PC += 2;
}
Possible Exceptions
Slot illegal instruction exception
resbank
Bank
0000000001011011 9/19 8/20
Res tore from Register Bank Restores the last register saved to a register bank.
Note
The issue cycle count is 19 when a bank overflow has occured and the registers
are restored from the stack.
Operation
void RESBANK (void)
{
int m; // Number of register bank to which a save was last performed.
if (BO == 0)
{
PR = Register_Bank[m].PR_BANK;
GBR = Register_Bank[m].GBR_BANK;
MACL = Register_Bank[m].MACL_BANK;
MACH = Register_Bank[m].MACH_BANK;
for (int i = 0; i <= 14; i++)
R[i] = Register_Bank[m].R_BANK[i];
}
else
{
for (int i = 0; i <= 14; i++)
{
R[i] = Read_32 (R[15]);
R[15] += 4;
}
PR = Read_32 (R[15]);
R[15] += 4;
GBR = Read_32 (R[15]);
R[15] += 4;
MACH = Read_32 (R[15]);
R[15] += 4;
MACL = Read_32 (R[15]);
R[15] += 4;
}
PC += 2;
}
rte
Delayed branch
SH1
0000000000101011 CO CO 1 1 6 6 1 5 5 4 4 5 5 4 5 4
Returns from an exception or interrupt handling routine by restoring the PC and
SR values. Program execution continues from the address specified
by the restored PC value.
PC and SR values are restored from SPC and SSR. The SR value
accessed by the instruction in the RTE delay slot is the value restored from SSR
by the RTE instruction. The SR and MD values defined prior to RTE execution are
used to fetch the instruction in the RTE delay slot.
PC and SR values are from the stack (R15).
Note
As this is a delayed branch instruction, the instruction following the RTE
instruction is executed before the branch destination instruction.
SR value accessed by the instruction in the RTE delay slot is
the value restored from SSR by the RTE instruction. The SR and MD values defined
prior to RTE execution are used to fetch the instruction in the RTE delay slot.
Operation
void RTE (void)
{
unsigned long temp = PC;
#if SH1 || SH2 || SH2A
PC = Read_32 (R[15]);
R[15] += 4;
SR = Read_32 (R[15]) & 0x000063F3;
R[15] += 4;
#elif SH3 || SH4 || SH4A
SR = SSR;
PC = SPC;
#endif
Delay_Slot (temp + 2);
}
Example
rte ! Returns to the original routine
add #8,r14 ! Executes ADD before branching
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
setrc Rn
Rn[11:0]
0100 mmmm 00010100 1 3
Set Repeat Count to RC Sets the repeat count to the SR register's RC counter. The bottom 12 bits of the
general register Rn are used as the repeat count.
Set repeat control flags to RF1, RF0 bits of the SR register. Use of the SETRC
instruction is subject to any limitations. Refer to the DSP Repeat (Loop)
Control section of the manual for more information.
Note
On the SH-DSP the latency of this instruction is 1 cycle.
Operation
void SETRC (int m)
{
long temp = (R[m] & 0x00000FFF) << 16;
SR &= 0x00000FF3;
SR |= temp;
RF1 = Repeat_Control_Flag1;
RF0 = Repeat_Control_Flag0;
PC += 2;
}
Example
ldrs start ! Set repeat start address to RS
ldre end ! Set repeat end address to RE
setrc r14 ! Repeat n times from <instruction A> to <instruction B>
...
start:
<instruction A>
...
...
...
end:
<instruction B>
...
setrc #imm
imm
10000010 iiiiiiii 1 3
Set Repeat Count to RC Sets the repeat count to the SR register's RC counter. The 8-bit immediate value
is zero-extended and used as the repeat count.
Set repeat control flags to RF1, RF0 bits of the SR register. Use of the SETRC
instruction is subject to any limitations. Refer to the DSP Repeat (Loop)
Control section of the manual for more information.
Note
On the SH-DSP the latency of this instruction is 1 cycle.
Operation
void SETRCI (int i)
{
long temp = ((long)i & 0x000000FF) << 16;
SR &= 0x00000FFF;
SR |= temp;
RF1 = Repeat_Control_Flag1;
RF0 = Repeat_Control_Flag0;
PC += 2;
}
Example
ldrs start ! Set repeat start address to RS
ldre end ! Set repeat end address to RE
setrc #32 ! Repeat 32 times from <instruction A> to <instruction B>
...
start:
<instruction A>
...
...
...
end:
<instruction B>
...
sets
1
0000000001011000 1
CO EX 1 1 1 1 1 1
Set S BitSets the S bit to 1.
Operation
void SETS (void)
{
S = 1;
PC += 2;
}
Example
sets ! Before execution: S = 0
! After execution: S = 1
sett
1
0000000000011000 1
MT EX 1 1 1 1 1 1 1 1 1 0 0 1 1 1
Set T BitSets the T bit to 1.
Operation
void SETT (void)
{
T = 1;
PC += 2;
}
Example
sett ! Before execution: T = 0
! After execution: T = 1
sleep
Sleep or standby
0000000000011011 CO CO 1 1 5 5 2 4 ud 3 3 0 0 4 4 ud
Sleep Places the CPU in the power-down state.
CPU retains its internal state, but immediately stops
executing instructions and waits for an interrupt request. When it receives an
interrupt request, the CPU exits the power-down state.
Note
SLEEP performance depends on the standby control register (STBCR). See
Power-Down Modes in the target product's hardware manual, for details.
Operation
void SLEEP (void)
{
Sleep_standby();
}
Example
sleep ! Enters power-down mode
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
stbank R0,@Rn
R0
0100 nnnn 11100001 7 6
St ore Register Bank R0 is transferred to the register bank entry indicated by the contents of
general register Rn. The register bank number and register stored in the bank
are specified by general register Rn.
Note
The architecture supports a maximum of 512 banks. However, the number of banks
differs depending on the product.
Operation
void STBANK (int n)
{
Write_Bank_32 (R[n], R[0])
PC += 2;
}
stc SR,Rn
SR
0000 nnnn 00000010 CO CO 1 1 2 2 1 2 1 1 1 2 2 1 2 1
Stores control register SR in the destination.
Note
This instruction is only usable in privileged mode. Issuing this instruction in
user mode will cause an illegal instruction exception.
Operation
void STCSR (int n)
{
R[n] = SR;
PC += 2;
}
Example
stc SR,r0 ! Before execution: r0 = 0xFFFFFFFF, SR = 0x00000000
! After execution: r0 = 0x00000000
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
stc.l SR,@-Rn
Rn
0100 nnnn 00000011 CO CO 1 1 2 2 1 2 1 2 2 2 2 1/2 2/2 1
Stores control register SR in the destination.
Note
This instruction is only usable in privileged mode. Issuing this instruction in
user mode will cause an illegal instruction exception.
Operation
void STCMSR (int n)
{
R[n] -= 4;
Write_32 (R[n], SR);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
stc TBR,Rn
TBR
0000 nnnn 01001010 1 1
Stores control register TBR in the destination.
Operation
void STCTBR (int n)
{
R[n] = TBR;
PC += 2;
}
stc GBR,Rn
GBR
0000 nnnn 00010010 CO LS 1 1 1 1 1 2 1 1 1 1 1 1 2 1
Stores control register GBR in the destination.
Note
This instruction can also be issued in user mode.
Operation
STCGBR (int n)
{
R[n] = GBR;
PC += 2;
}
stc.l GBR,@-Rn
Rn
0100 nnnn 00010011 CO LS 1 1 1 1 1 2 1 2 2 1 1 1/2 2/2 1
Stores control register GBR in the destination.
Note
This instruction can also be issued in user mode.
Operation
void STCMGBR (int n)
{
R[n] -= 4;
Write_32 (R[n], GBR);
PC += 2;
}
Example
stc.l GBR,@-r15 ! Before execution: r15 = 0x10000004
! After execution: r15 = 0x10000000, @r15 = GBR
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
stc VBR,Rn
VBR
0000 nnnn 00100010 CO LS 1 1 1 1 1 2 1 1 1 1 1 1 2 1
Stores control register VBR in the destination.
Operation
void STCVBR (int n)
{
R[n] = VBR;
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
stc.l VBR,@-Rn
Rn
0100 nnnn 00100011 CO LS 1 1 1 1 1 2 1 2 2 1 1 1/2 2/2 1
Stores control register VBR in the destination.
Operation
void STCMVBR (int n)
{
R[n] -= 4;
Write_32 (R[n], VBR);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
stc MOD,Rn
MOD
0000 nnnn 01010010 1 1
Stores control register MOD in the destination.
Operation
void STCMOD (int n)
{
R[n] = MOD;
PC += 2;
}
stc.l MOD,@-Rn
Rn
0100 nnnn 01010011 1 1/2
Stores control register MOD in the destination.
Note
On the SH-DSP the latency of this instruction is 2 cycles.
Operation
void STCMMOD (int n)
{
R[n] -= 4;
Write_32 (R[n], MOD);
PC += 2;
}
Possible Exceptions
Data address error
stc RE,Rn
RE
0000 nnnn 01110010 1 1
Stores control register RE in the destination.
Operation
void STCRE (int n)
{
R[n] = RE;
PC += 2;
}
stc.l RE,@-Rn
Rn
0100 nnnn 01110011 1 1/2
Stores control register RE in the destination.
Note
On the SH-DSP the latency of this instruction is 2 cycles.
Operation
void STCMRE (int n)
{
R[n] -= 4;
Write_32 (R[n], RE);
PC += 2;
}
Possible Exceptions
Data address error
stc RS,Rn
RS
0000 nnnn 01100010 1 1
Stores control register RS in the destination.
Operation
void STCRS (int n)
{
R[n] = RS;
PC += 2;
}
stc.l RS,@-Rn
Rn
0100 nnnn 01100011 1 1/2
Stores control register RS in the destination.
Note
On the SH-DSP the latency of this instruction is 2 cycles.
Operation
void STCMRS (int n)
{
R[n] -= 4;
Write_32 (R[n], RS);
PC += 2;
}
Possible Exceptions
Data address error
stc SGR,Rn
SGR
0000 nnnn 00111010 CO LS 3 1 3 1
Stores control register SGR in the destination.
Operation
void STCSGR (int n)
{
R[n] = SGR;
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
stc.l SGR,@-Rn
Rn
0100 nnnn 00110010 CO LS 3 1 3/3 1
Stores control register SGR in the destination.
Operation
void STCMSGR (int n)
{
R[n] -= 4;
Write_32 (R[n], SGR);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
stc SSR,Rn
SSR
0000 nnnn 00110010 CO LS 1 2 1 1 2 1
Stores control register SSR in the destination.
Operation
void STCSSR (int n)
{
R[n] = SSR;
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
stc.l SSR,@-Rn
Rn
0100 nnnn 00110011 CO LS 1 2 1 1/2 2 1
Stores control register SSR in the destination.
Operation
void STCMSSR (int n)
{
R[n] -= 4;
Write_32 (R[n], SSR);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
stc SPC,Rn
SPC
0000 nnnn 01000010 CO LS 1 2 1 1 2 1
Stores control register SPC in the destination.
Operation
void STCSPC (int n)
{
R[n] = SPC;
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
stc.l SPC,@-Rn
Rn
0100 nnnn 01000011 CO LS 2 1 2/2 1
Stores control register SPC in the destination.
Operation
void STCMSPC (int n)
{
R[n] -= 4;
Write_32 (R[n], SPC);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
stc DBR,Rn
DBR
0000 nnnn 11111010 CO LS 2 1 2 1
Stores control register DBR in the destination.
Operation
void STCDBR (int n)
{
R[n] = DBR;
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
stc.l DBR,@-Rn
Rn
0100 nnnn 11110010 CO LS 2 1 2/2 1
Stores control register DBR in the destination.
Operation
void STCMDBR (int n)
{
R[n] -= 4;
Write_32 (R[n], DBR);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
stc Rm_BANK,Rn
Rm_BANK
0000 nnnn 1 mmm 0010 CO LS 1 2 1 1 2 1
Stores a banked general register in the destination. Rn_BANK0 is accessed when
the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.
Operation
void STCRm_BANK (int n)
{
R[n] = Rm_BANK;
PC += 2;
}
Possible Exceptions
General illegal instruction exception
Slot illegal instruction exception
stc.l Rm_BANK,@-Rn
Rn
0100 nnnn 1 mmm 0011 CO LS 2 2 1 2 2/2 1
Stores a banked general register in the destination. Rn_BANK0 is accessed when
the RB bit in the SR register is 1, and Rn_BANK1 is accessed when this bit is 0.
Operation
void STCMRm_BANK (int n)
{
R[n] -= 4;
Write_32 (R[n], Rm_BANK);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
General illegal instruction exception
Slot illegal instruction exception
sts MACH,Rn
MACH
0000 nnnn 00001010 CO LS 1 1 1 1 1 1 1 1 1 2 2 1 3 1
Stores system register MACH in the destination.
Note
On SH1, the value of bit 9 is transferred to and stored in the higher 22 bits
(bits 31 to 10) of the destination.
MAC * is followed by an STS.L MAC *,@-Rn instruction, the
latency of the LDS to MAC * is 4 cycles.
Operation
void STSMACH (int n)
{
R[n] = MACH;
#if SH1
if ((R[n] & 0x00000200) == 0)
R[n] &= 0x000003FF;
else
R[n] |= 0xFFFFFC00;
#endif
PC += 2;
}
Example
sts MACH,r0 ! Before execution: r0 = 0xFFFFFFFF, MACH = 0x00000000
! After execution: r0 = 0x00000000
sts.l MACH,@-Rn
Rn
0100 nnnn 00000010 CO LS 1 1 1 1 1 1 1 1 1 1 1 1 1/1 1
Stores system register MACH in the destination.
Note
On SH1, the value of bit 9 is transferred to and stored in the higher 22 bits
(bits 31 to 10) of the destination.
MAC * is followed by an STS.L MAC *,@-Rn instruction, the
latency of the LDS to MAC * is 4 cycles.
Operation
void STSMMACH (int n)
{
R[n] -= 4;
#if SH1
if ((MACH & 0x00000200) == 0)
Write_32 (R[n], MACH & 0x000003FF);
else
Write_32 (R[n], MACH | 0xFFFFFC00)
#else
Write_32 (R[n], MACH);
#endif
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
sts MACL,Rn
MACL
0000 nnnn 00011010 CO LS 1 1 1 1 1 1 1 1 1 2 2 1 3 1
Stores system register MACL in the destination.
Note
On SH4, when an LDS to MAC * is followed by an STS.L MAC *,@-Rn instruction, the
latency of the LDS to MAC * is 4 cycles.
Operation
void STSMACL (int n)
{
R[n] = MACL;
PC += 2;
}
sts.l MACL,@-Rn
Rn
0100 nnnn 00010010 CO LS 1 1 1 1 1 1 1 1 1 1 1 1 1/1 1
Stores system register MACL in the destination.
Note
On SH4, when an LDS to MAC * is followed by an STS.L MAC *,@-Rn instruction, the
latency of the LDS to MAC * is 4 cycles.
Operation
void STSMMACL (int n)
{
R[n] -= 4;
Write_32 (R[n], MACL);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
sts PR,Rn
PR
0000 nnnn 00101010 CO LS 1 1 1 1 1 2 1 1 1 1 1 1 2 1
Stores system register PR in the destination.
Operation
void STSPR (int n)
{
R[n] = PR;
PC += 2;
}
sts.l PR,@-Rn
Rn
0100 nnnn 00100010 CO LS 1 1 1 1 1 2 1 1 1 1 1 1 2/2 1
Stores system register PR in the destination.
Operation
void STSMPR (int n)
{
R[n] -= 4;
Write_32 (R[n], PR);
PC += 2;
}
Example
sts.l PR,@-r15 ! Before execution: r15 = 0x10000004
! After execution: r15 = 0x10000000, @r15 = PR
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Initial page write exception
Data address error
sts DSR,Rn
DSR
0000 nnnn 01101010 1 1
St ore from FPU S ystem RegisterStores DSP register DSR in the destination.
Operation
void STSDSR (int n)
{
R[n] = DSR;
PC += 2;
}
sts.l DSR,@-Rn
Rn
0100 nnnn 01100010 1 1
St ore from FPU S ystem RegisterStores DSP register DSR in the destination.
Operation
void STSMDSR (int n)
{
R[n] -= 4;
Write_32 (R[n], DSR);
PC += 2;
}
Possible Exceptions
Data address error
sts A0,Rn
A0
0000 nnnn 01111010 1 1
Stores DSP register A0 in the destination.
Operation
void STSA0 (int n)
{
R[n] = A0;
PC += 2;
}
sts.l A0,@-Rn
Rn
0100 nnnn 01110010 1 1
Stores DSP register A0 in the destination.
Operation
void STSMA0 (int n)
{
R[n] -= 4;
Write_32 (R[n], A0);
PC += 2;
}
Possible Exceptions
Data address error
sts X0,Rn
X0
0000 nnnn 10001010 1 1
Stores DSP register X0 in the destination.
Operation
void STSX0 (int n)
{
R[n] = X0;
PC += 2;
}
sts.l X0,@-Rn
Rn
0100 nnnn 10000010 1 1
Stores DSP register X0 in the destination.
Operation
void STSMX0 (int n)
{
R[n] -= 4;
Write_32 (R[n], X0);
PC += 2;
}
Possible Exceptions
Data address error
sts X1,Rn
X1
0000 nnnn 10011010 1 1
Stores DSP register X1 in the destination.
Operation
void STSX1 (int n)
{
R[n] = X1;
PC += 2;
}
sts.l X1,@-Rn
Rn
0100 nnnn 10010010 1 1
Stores DSP register X1 in the destination.
Operation
void STSMX1 (int n)
{
R[n] -= 4;
Write_32 (R[n], X1);
PC += 2;
}
Possible Exceptions
Data address error
sts Y0,Rn
Y0
0000 nnnn 10101010 1 1
Stores DSP register Y0 in the destination.
Operation
void STSY0 (int n)
{
R[n] = Y0;
PC += 2;
}
sts.l Y0,@-Rn
Rn
0100 nnnn 10100010 1 1
Stores DSP register Y0 in the destination.
Operation
void STSMY0 (int n)
{
R[n] -= 4;
Write_32 (R[n], Y0);
PC += 2;
}
Possible Exceptions
Data address error
sts Y1,Rn
Y1
0000 nnnn 10111010 1 1
Stores DSP register Y1 in the destination.
Operation
void STSY1 (int n)
{
R[n] = Y1;
PC += 2;
}
sts.l Y1,@-Rn
Rn
0100 nnnn 10110010 1 1
Stores DSP register Y1 in the destination.
Operation
void STSMY1 (int n)
{
R[n] -= 4;
Write_32 (R[n], Y1);
PC += 2;
}
Possible Exceptions
Data address error
synco
Prevents the next instruction from being issued until instructions issued before this instruction has been completed.
0000000010101011 CO ud ud
Sync hronize Data O perationThis instruction is used to synchronize data operations. When this instruction
is executed, the subsequent bus accesses are not executed until the execution of
all preceding bus accesses has been completed.
Note
The SYNCO instruction can not guarantee the ordering of receipt timing which is
notified by the memory-mapped peripheral resources through the method except bus
when the register is changed by bus accesses. Refer to the description of each
registers to guarantee this ordering.
Operation
void SYNCO (void)
{
synchronize_data_operaiton ();
PC += 2;
}
trapa #imm
SH1
11000011 iiiiiiii CO CO 2 2 5 5 2 7 14 8 8 6 6 8 7 13
Trap A lwaysStarts trap exception handling.
SH1, SH2 and SH2A:
PC and SR values are stored on the stack, and the program branches to an
address specified by the vector. The vector is a memory address obtained by
zero-extending the 8-bit immediate data and then quadrupling it. The PC is the
start address of the next instruction. TRAPA and RTE are both used together for
system calls.
PC + 2), SR , and R15 are saved to SPC, SSR and SGR, and 8-bit
immediate data is stored in the TRA register (bits 9 to 2). The processor mode
is switched to privileged mode (the MD bit in SR is set to 1), and the BL bit
and RB bit in SR are set to 1. As a result, exception and interrupt requests
are masked (not accepted), and the BANK1 registers (R0_BANK1 to R7_BANK1) are
selected. Exception code 0x160 is written to the EXPEVT register (bits 11 to 0).
The program branches to address (VBR + 0x00000100), indicated by the sum of the
VBR register contents and offset 0x00000100.
Note
Some SH4 implementations have a hardware bug which restricts the instructions
that should follow this instruction for safe operation. There are two
recommended workarounds:
Put 8 NOP instructions following the TRAPA instruction.
Put 5 "OR R0,R0" instructions following the TRAPA instruction
FPU related hardware bug which
affects this instruction. The recommended workaround is to align the addresses
of trapa handlers to 4 bytes and not to place any FPU or FPU related
instructions at addresses 4n + 2 in the handler.
Operation
void TRAPA (int i)
{
int imm = (0x000000FF & i);
#if SH1 || SH2 || SH2A
R[15] -= 4;
Write_32 (R[15], SR);
R[15] -= 4;
Write_32 (R[15], PC + 2);
PC = Read_32 (VBR + (imm << 2));
#elif SH3 || SH4 || SH4A
TRA = imm << 2;
SSR = SR;
SPC = PC + 2;
SGR = R15;
SR.MD = 1;
SR.BL = 1;
SR.RB = 1;
EXPEVT = 0x00000160;
PC = VBR + 0x00000100;
#endif
}
Example
vbr +0x80
trapa #0x20 ! Branches to an address specified by data in address VBR + 0x80
tst #0,r0 ! ← Return address from the trap routine (stacked PC value)
10000000 0
10000000 2
10000000 4
Possible Exceptions
Unconditional trap
Slot illegal instruction exception
32 Bit Floating-Point Data Transfer Instructions (FPSCR.SZ = 0)
fmov FRm,FRn
FRm
1111 nnnn mmmm 1100 LS LS 1 1 1 1 1 1 0 1 0 1
F loating-point Mov eTransfers FRm contents to FRn.
Operation
void FMOV (int m, int n)
{
FR[n] = FR[m];
PC += 2;
}
fmov.s @Rm,FRn
(Rm)
1111 nnnn mmmm 1000 LS LS 1 1 1 1 1 1 0/2 1 2 1
F loating-point Mov eTransfers contents of memory at address indicated by Rm to FRn.
Operation
void FMOV_LOAD (int m, int n)
{
FR[n] = Read_32 (R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov.s FRm,@Rn
FRm
1111 nnnn mmmm 1010 LS LS 1 1 1 1 1 1 0 1 1 1
F loating-point Mov eTransfers FRm contents to memory at address indicated by Rn.
Operation
void FMOV_STORE (int m, int n)
{
Write_32 (R[n], FR[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov.s @Rm+,FRn
(Rm)
1111 nnnn mmmm 1001 LS LS 1 1 1 1 1 1 1/2 1 1/2 1
F loating-point Mov eTransfers contents of memory at address indicated by Rm to FRn, and adds 4 to
Rm.
Operation
void FMOV_RESTORE (int m, int n)
{
FR[n] = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov.s FRm,@-Rn
Rn
1111 nnnn mmmm 1011 LS LS 1 1 1 1 1 1 1/0 1 1/1 1
F loating-point Mov eSubtracts 4 from Rn, and transfers FRm contents to memory at address indicated
by resulting Rn value.
Operation
void FMOV_SAVE (int m, int n)
{
Write_32 (R[n] - 4, FR[m]);
R[n] -= 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov.s @(R0,Rm),FRn
(R0
1111 nnnn mmmm 0110 LS LS 1 1 1 1 1 1 0/2 1 2 1
F loating-point Mov eTransfers contents of memory at address indicated by (R0 + Rm) to FRn.
Operation
void FMOV_INDEX_LOAD (int m, int n)
{
FR[n] = Read_32 (R[0] + R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov.s FRm,@(R0,Rn)
FRm
1111 nnnn mmmm 0111 LS LS 1 1 1 1 1 1 0 1 1 1
F loating-point Mov eTransfers FRm contents to memory at address indicated by (R0 + Rn).
Operation
void FMOV_INDEX_STORE (int m, int n)
{
Write_32 (R[0] + R[n], FR[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov.s @(disp12,Rm),FRn
(disp
0011 nnnn mmmm 00010111 dddddddddddd 1 0/2
F loating-point Mov eTransfers memory contents at the address indicated by (disp + Rn) to FRn.
Operation
void FMOV_INDEX_DISP12_LOAD (int m, int n, int d)
{
long disp = (0x00000FFF & (long)d);
FR[n] = Read_32 (R[m] + (disp << 2));
PC += 4;
}
Possible Exceptions
Data address error
fmov.s FRm,@(disp12,Rn)
FRm
0011 nnnn mmmm 00010011 dddddddddddd 1 0
F loating-point Mov eTransfers FRm contents to memory at the address indicated by (disp + Rn).
Operation
void FMOV_INDEX_DISP12_STORE (int m, int n, int d)
{
long disp = (0x00000FFF & (long)d);
Write_32 (R[n] + (disp << 2), FR[m]);
PC += 4;
}
Possible Exceptions
Data address error
64 Bit Floating-Point Data Transfer Instructions (FPSCR.SZ = 1)
fmov DRm,DRn
DRm
1111 nnn 0 mmm 01100 LS LS 2 1 1 1 0 1
F loating-point Mov eTransfers DRm contents to DRn.
Operation
void FMOV_DR (int m, int n)
{
DR[n >> 1] = DR[m >> 1];
PC += 2;
}
fmov DRm,XDn
DRm
1111 nnn 1 mmm 01100 LS LS 1 1 0 1
F loating-point Mov e ExtensionTransfers DRm contents to XDn.
Operation
void FMOV_DRXD (int m, int n)
{
XD[n >> 1] = DR[m >> 1];
PC += 2;
}
fmov XDm,DRn
XDm
1111 nnn 0 mmm 11100 LS LS 1 1 0 1
F loating-point Mov e ExtensionTransfers XDm contents to DRn.
Operation
void FMOV_XDDR (int m, int n)
{
DR[n >> 1] = XD[m >> 1];
PC += 2;
}
fmov XDm,XDn
XDm
1111 nnn 1 mmm 11100 LS LS 1 1 0 1
F loating-point Mov e ExtensionTransfers XDm contents to XDn.
Operation
void FMOV_XDXD (int m, int n)
{
XD[n >> 1] = XD[m >> 1];
PC += 2;
}
fmov @Rm,DRn
(Rm)
1111 nnn 0 mmmm 1000 LS LS 2 1 1 0/4 2 1
F loating-point Mov eTransfers contents of memory at address indicated by Rm to DRn.
Operation
void FMOV_LOAD_DR (int m, int n)
{
DR[n >> 1] = Read_64 (R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov @Rm,XDn
(Rm)
1111 nnn 1 mmmm 1000 LS LS 1 1 2 1
F loating-point Mov e ExtensionTransfers contents of memory at address indicated by Rm to XDn.
Operation
void FMOV_LOAD_XD (int m, int n)
{
XD[n >> 1] = Read_64 (R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov DRm,@Rn
DRm
1111 nnnn mmm 01010 LS LS 2 1 1 0 1 1
F loating-point Mov eTransfers DRm contents to memory at address indicated by Rn.
Operation
void FMOV_STORE_DR (int m, int n)
{
Write_64 (R[n], DR[m >> 1]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov XDm,@Rn
XDm
1111 nnnn mmm 11010 LS LS 1 1 1 1
F loating-point Mov e ExtensionTransfers contents of memory at address indicated by (R0 + Rm) to XDn.
Operation
void FMOV_STORE_XD (int m, int n)
{
Write_64 (R[n], XD[m >> 1]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov @Rm+,DRn
(Rm)
1111 nnn 0 mmmm 1001 LS LS 2 1 1 1/4 1/2 1
F loating-point Mov eTransfers contents of memory at address indicated by Rm to DRn, and adds 8 to
Rm.
Operation
void FMOV_RESTORE_DR (int m, int n)
{
DR[n >> 1] = Read_64 (R[m]);
R[m] += 8;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov @Rm+,XDn
(Rm)
1111 nnn 1 mmmm 1001 LS LS 1 1 1/2 1
F loating-point Mov e ExtensionTransfers contents of memory at address indicated by Rm to XDn, and adds 8 to
Rm.
Operation
void FMOV_RESTORE_XD (int m, int n)
{
XD[n >> 1] = Read_64 (R[m]);
R[m] += 8;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov DRm,@-Rn
Rn
1111 nnnn mmm 01011 LS LS 2 1 1 0/1 1/1 1
F loating-point Mov eSubtracts 8 from Rn, and transfers DRm contents to memory at address indicated
by resulting Rn value.
Operation
void FMOV_SAVE_DR (int m, int n)
{
Write_64 (R[n] - 8, DR[m >> 1]);
R[n] -= 8;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov XDm,@-Rn
Rn
1111 nnnn mmm 11011 LS LS 1 1 1/1 1
F loating-point Mov e ExtensionSubtracts 8 from Rn, and transfers XDm contents to memory at address indicated
by resulting Rn value.
Operation
void FMOV_SAVE_XD (int m, int n)
{
Write_64 (R[n] - 8, XD[m >> 1]);
R[n] -= 8;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov @(R0,Rm),DRn
(R0
1111 nnn 0 mmmm 0110 LS LS 2 1 1 0/4 2 1
F loating-point Mov eTransfers contents of memory at address indicated by (R0 + Rm) to DRn.
Operation
void FMOV_INDEX_LOAD_DR (int m, int n)
{
DR[n >> 1] = Read_64 (R[0] + R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov @(R0,Rm),XDn
(R0
1111 nnn 1 mmmm 0110 LS LS 1 1 2 1
F loating-point Mov e ExtensionTransfers contents of memory at address indicated by (R0 + Rm) to XDn.
Operation
void FMOV_INDEX_LOAD_XD (int m, int n)
{
XD[n >> 1] = Read_64 (R[0] + R[m]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
fmov DRm,@(R0,Rn)
DRm
1111 nnnn mmm 00111 LS LS 2 1 1 0 1 1
F loating-point Mov eTransfers DRm contents to memory at address indicated by (R0 + Rn).
Operation
void FMOV_INDEX_STORE_DR (int m, int n)
{
Write_64 (R[0] + R[n], DR[m >> 1]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov XDm,@(R0,Rn)
XDm
1111 nnnn mmm 10111 LS LS 1 1 1 1
F loating-point Mov e ExtensionTransfers XDm contents to memory at address indicated by (R0 + Rn).
Operation
void FMOV_INDEX_STORE_XD (int m, int n)
{
Write_64 (R[0] + R[n], XD[m >> 1]);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
fmov.d @(disp12,Rm),DRn
(disp
0011 nnn 0 mmmm 00010111 dddddddddddd 2 0/4
F loating-point Mov eTransfers memory contents at the address indicated by (disp + Rn) to DRn.
Operation
void FMOV_INDEX_DISP12_LOAD_DR (int m, int n, int d)
{
long disp = (0x00000FFF & (long)d);
DR[n >> 1] = Read_64 (R[m] + (disp << 3));
PC += 4;
}
Possible Exceptions
Data address error
fmov.d DRm,@(disp12,Rn)
DRm
0011 nnnn mmm 000010011 dddddddddddd 2 0
F loating-point Mov eTransfers DRm contents to memory at the address indicated by (disp + Rn).
Operation
void FMOV_INDEX_DISP12_STORE_DR (int m, int n, int d)
{
long disp = (0x00000FFF & (long)d);
Write_64 (R[n] + (disp << 3), DR[m >> 1]);
PC += 4;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
Floating-Point Single-Precision Instructions (FPSCR.PR = 0)
fldi0 FRn
0x00000000
1111 nnnn 10001101 LS LS 1 1 1 1 1 1 0 1 0 1
F loating-point L oad I mmediate 0 .0When FPSCR .PR = 0, this instruction loads floating-point 0.0 (0x00000000) into
FRn.FPSCR .PR = 1, the instruction is handled as an illegal instruction.
Operation
void FLDI0 (int n)
{
FR[n] = 0x00000000;
PC += 2;
}
fldi1 FRn
0x3F800000
1111 nnnn 10011101 LS LS 1 1 1 1 1 1 0 1 0 1
F loating-point L oad I mmediate 1 .0When FPSCR .PR = 0, this instruction loads floating-point 1.0 (0x3F800000) into
FRn.PR = 1, the instruction is handled as an illegal instruction.
Operation
void FLDI1 (int n)
{
FR[n] = 0x3F800000;
PC += 2;
}
flds FRm,FPUL
FRm
1111 mmmm 00011101 LS LS 1 1 1 1 1 1 0 1 0 1
F loating-point L oad to S ystem RegisterTransfers the contents of floating-point register FRm into system register FPUL .
Operation
void FLDS (int m)
{
FPUL = FR[m];
PC += 2;
}
fsts FPUL,FRn
FPUL
1111 nnnn 00001101 LS LS 1 1 1 1 1 1 0 1 0 1
F loating-point St ore S ystem RegisterTransfers the contents of system register FPUL to floating-point register FRn.
Operation
void FSTS (int n)
{
FR[n] = FPUL;
PC += 2;
}
fabs FRn
FRn
1111 nnnn 01011101 LS LS 1 1 1 1 1 1 0 1 0 1
F loating-point Abs olute ValueClears the most significant bit of the contents of floating-point register FRn
to 0, and stores the result in FRn.
Note
The cause and flag fields in FPSCR are not updated.
PR setting before this instruction.
Operation
void FABS (int n)
{
FR[n] = FR[n] & 0x7FFFFFFFF;
PC += 2;
}
fneg FRn
FRn
1111 nnnn 01001101 LS LS 1 1 1 1 1 1 0 1 0 1
F loating-point Neg ate ValueInverts the most significant bit (sign bit) of the contents of floating-point
register FRn, and stores the result in FRn.
Note
The cause and flag fields in FPSCR are not updated.
PR setting before this instruction.
Operation
void FNEG (int n)
{
FR[n] = -FR[n];
PC += 2;
}
fadd FRm,FRn
FRn
1111 nnnn mmmm 0000 FE FE 1 1 1 1 1 1 3 1 3/4 1
F loating-point Add Arithmetically adds the two single-precision floating-point numbers in FRn and
FRm, and stores the result in FRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and FRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Note
SH2E and SH3E support only invalid operation (V ) and division by zero
(Z ) exception flags.
Operation
void FADD (int m, int n)
{
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case NORM:
normal_faddsub (m, n, ADD);
break;
case PZERO:
case NZERO:
register_copy (m, n);
break;
default:
break;
}
break;
case PZERO:
switch (data_type_of (n))
{
case NZERO:
zero (n, 0);
break;
default:
break;
}
break;
case NZERO:
break;
case PINF:
switch (data_type_of (n))
{
case NINF:
invalid (n);
break;
default:
inf (n, 0);
break;
}
break;
case NINF:
switch (data_type_of (n))
{
case PINF:
invalid (n);
break;
default:
inf (n, 1);
break;
}
break;
}
}
Possible Exceptions
FPU Error
Invalid Operation
Overflow
Generation of overflow-exception traps
FRn and FRm have the same sign and the exponent of at least one value is 0xFE
Underflow
Generation of underflow-exception traps
FRn and FRm have different signs and neither has an exponent greater than 0x18
Inexact
fsub FRm,FRn
FRn
1111 nnnn mmmm 0001 FE FE 1 1 1 1 1 1 3 1 3/4 1
F loating-point Sub tractArithmetically subtracts the single-precision floating-point number in FRm from
the single-precision floating-point number in FRn, and stores the result in FRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and FRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Note
SH2E and SH3E support only invalid operation (V ) and division by zero
(Z ) exception flags.
Operation
void FSUB (int m, int n)
{
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case NORM:
normal_faddsub (m, n, SUB);
break;
case PZERO:
case NZERO:
register_copy (m, n);
FR[n] = -FR[n];
break;
default:
break;
}
break;
case PZERO:
break;
case NZERO:
switch (data_type_of (n))
{
case NZERO:
zero (n, 0);
break;
default:
break;
}
break;
case PINF:
switch (data_type_of (n))
{
case PINF:
invalid (n);
break;
default:
inf (n, 1);
break;
}
break;
case NINF:
switch (data_type_of (n))
{
case NINF:
invalid (n);
break;
default:
inf (n, 0);
break;
}
break;
}
}
Possible Exceptions
FPU Error
Invalid Operation
Overflow
Generation of overflow-exception traps
FRn and FRm have the same sign and the exponent of at least one value is 0xFE
Underflow
Generation of underflow-exception traps
FRn and FRm have different signs and neither has an exponent greater than 0x18
Inexact
fmul FRm,FRn
FRn
1111 nnnn mmmm 0010 FE FE 1 1 1 1 1 1 3 1 3/4 1
F loating-point Mul tiplyArithmetically multiplies the two single-precision floating-point numbers in
FRn and FRm, and stores the result in FRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and FRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Note
SH2E and SH3E support only invalid operation (V ) and division by zero
(Z ) exception flags.
Operation
void FMUL (int m, int n)
{
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
default:
normal_fmul (m, n);
break;
}
break;
case PZERO:
case NZERO:
switch (data_type_of (n))
{
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n,sign_of (m) ^ sign_of (n));
break;
}
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
default:
inf (n, sign_of (m) ^ sign_of (n));
break
}
break;
}
}
Possible Exceptions
FPU Error
Invalid Operation
Overflow
Generation of overflow-exception traps
(exponent of FRn) + (exponent of FRm) - 0x7F is not less than 0xFE
Underflow
Generation of underflow-exception traps
When both FRn and FRm are normalized numbers:
(exponent of FRn) + (exponent of FRm) - 0x7F is not more than 0x00
When at least FRn or FRm is not a normalized number:
(exponent of FRn) + (exponent of FRm) - 0x7F is not more than 0x18
Inexact
fmac FR0,FRm,FRn
FR0
1111 nnnn mmmm 1110 FE FE 1 1 1 1 1 1 3 1 3/4 1
F loating-point M ultiply and Ac cumulateArithmetically multiplies the two single-precision floating-point numbers in
FR0 and FRm, arithmetically adds the contents of FRn, and stores the result in
FRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and FRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Note
SH2E and SH3E support only invalid operation (V ) and division by zero
(Z ) exception flags.
Operation
void FMAC (int m, int n)
{
PC += 2;
clear_cause ();
if (FPSCR_PR == 1)
undefined_operation ();
else if (data_type_of (0) == sNaN
|| data_type_of (m) == sNaN
|| data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (0) == qNaN || data_type_of (m) == qNaN)
qnan (n);
else if (data_type_of (0) == DENORM || data_type_of (m) == DENORM)
set_E ();
else
switch (data_type_of (0))
{
case NORM:
switch (data_type_of (m))
{
case PZERO:
case NZERO:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case qNaN:
qnan (n);
break;
case PZERO:
case NZERO:
zero (n, sign_of (0) ^ sign_of (m) ^ sign_of (n));
break;
default:
break;
}
case PINF:
case NINF:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case qNaN:
qnan (n);
break;
case PINF:
case NINF:
if (sign_of (0) ^ sign_of (m) ^ sign_of (n))
invalid (n);
else
inf (n, sign_of (0) ^ sign_of (m));
break;
default:
inf (n, sign_of (0) ^ sign_of (m));
break;
}
case NORM:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case qNaN:
qnan (n);
break;
case PINF:
case NINF:
inf (n, sign_of (n));
break;
case PZERO:
case NZERO:
case NORM:
normal_fmac (m, n);
break;
}
break;
case PZERO:
case NZERO:
switch (data_type_of (m))
{
case PINF:
case NINF:
invalid (n);
break;
case PZERO:
case NZERO:
case NORM:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case qNaN:
qnan (n);
break;
case PZERO:
case NZERO:
zero (n, sign_of (0) ^ sign_of (m) ^ sign_of (n));
break;
default:
break;
}
break;
}
break;
case PINF:
case NINF:
switch (data_type_of (m))
{
case PZERO:
case NZERO:
invalid (n);
break;
default:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case qNaN:
qnan(n);
break;
default:
inf (n, sign_of (0) ^ sign_of (m) ^ sign_of (n));
break
}
break;
}
break;
}
}
}
void normal_fmac (int m, int n)
{
union
{
int double x;
int l[4];
} dstx, tmpx;
float dstf, srcf;
if (data_type_of (n) == PZERO || data_type_of (n) == NZERO)
srcf = 0.0; // flush denormalized value
else
srcf = FR[n];
tmpx.x = FR[0]; // convert single to int double
tmpx.x *= FR[m]; //exact product
dstx.x = tmpx.x + srcf;
if ((dstx.x == srcf && tmpx.x != 0.0)
|| (dstx.x == tmpx.x && srcf != 0.0))
{
set_I ();
if (sign_of (0) ^ sign_of (m) ^ sign_of (n))
{
dstx.l[3] -= 1; // correct result
if (dstx.l[3] == 0xFFFFFFFF)
dstx.l[2] -= 1;
if (dstx.l[2] == 0xFFFFFFFF)
dstx.l[1] -= 1;
if (dstx.l[1] == 0xFFFFFFFF)
dstx.l[0] -= 1;
}
else
dstx.l[3] |= 1
}
if ((dstx.l[1] & 0x01FFFFFF) || dstx.l[2] || dstx.l[3])
set_I();
if(FPSCR_RM == 1)
{
dstx.l[1] &= 0xFE000000; // round toward zero
dstx.l[2] = 0x00000000;
dstx.l[3] = 0x00000000;
}
dstf = dstx.x;
check_single_exception (&FR[n], dstf);
}
Possible Exceptions
FPU Error
Invalid Operation
Overflow
Generation of overflow-exception traps
At least one of the following results is not less than 0xFD:
(exponent of FR0) + (exponent of FRm)
(exponent of FRn)
Underflow
Generation of underflow-exception traps
At least one of the following results is not more than 0x2E:
(exponent of FR0) + (exponent of FRm)
(exponent of FRn)
Inexact
fdiv FRm,FRn
FRn
1111 nnnn mmmm 0011 FE FE 1 1 1 1 1 13 12 13 12/13 14
F loating-point Div ideArithmetically divides the single-precision floating-point number in FRn by the
single-precision floating-point number in FRm, and stores the result in FRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and FRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Note
SH2E and SH3E support only invalid operation (V ) and division by zero
(Z ) exception flags.
Operation
void FDIV (int m, int n)
{
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case DENORM:
set_E ();
break;
default:
normal_fdiv_single (m, n);
break;
}
break;
case PZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
case NINF:
break;
default:
dz (n, sign_of (m) ^ sign_of (n));
break;
}
break;
case NZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
inf (n, 1);
break;
case NINF:
inf (n, 0);
break;
default:
dz (FR[n], sign_of (m) ^ sign_of (n));
break;
}
break;
case DENORM:
set_E ();
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n, sign_of (m) ^ sign_of (n));
break;
}
break;
}
}
void normal_fdiv_single (int m, int n)
{
union
{
float f;
int l;
} dstf, tmpf;
union
{
double d;
int l[2];
} tmpd;
tmpf.f = FR[n]; // save destination value
dstf.f /= FR[m]; // round toward nearest or even
tmpd.d = dstf.f; // convert single to double
tmpd.d *= FR[m];
if (tmpf.f != tmpd.d)
set_I ();
if (tmpf.f < tmpd.d && FPSCR_RM == 1)
dstf.l -= 1; // round toward zero
check_single_exception (&FR[n], dstf.f);
}
Possible Exceptions
FPU Error
Invalid Operation
Division by zero
Overflow
Generation of overflow-exception traps
(exponent of FRn) - (exponent of FRm) + 0x7F is not less than 0xFF
Underflow
Generation of underflow-exception traps
(exponent of FRn) - (exponent of FRm) + 0x7F is not more than 0x01
Inexact
fsqrt FRn
FRn 1111 nnnn 01101101 FE FE 1 1 1 1 11 13 11/12 30
F loating-point Sq uare R oot Finds the arithmetical square root of the single-precision floating-point number
in FRn, and stores the result in FRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When an exception occurs, correct
exception information is reflected in FPSCR .cause and FPSCR .flag and FRn is not
updated. Appropriate processing should therefore be performed by software.
Operation result special cases
Note
SH3E supports only invalid operation (V ) and division by zero
(Z ) exception flags.
Operation
void FSQRT (int n)
{
PC += 2;
clear_cause ();
switch (data_type_of (n))
{
case NORM:
if (sign_of (n) == 0)
normal_fsqrt_single (n);
else
invalid (n);
break;
case DENORM:
if (sign_of (n) == 0)
set_E ();
else
invalid (n);
break;
case PZERO:
case NZERO:
case PINF:
break;
case NINF:
invalid (n);
break;
case qNAN:
qnan (n);
break;
case sNAN:
invalid (n);
break;
}
}
void normal_fsqrt_single (int n)
{
union
{
float f;
int l;
} dstf, tmpf;
union
{
double d;
int l[2];
} tmpd;
tmpf.f = FR[n]; // save destination value
dstf.f = sqrt (FR[n]); // round toward nearest or even
tmpd.d = dstf.f; // convert single to double
tmpd.d *= dstf.f;
if (tmpf.f != tmpd.d)
set_I ();
if (tmpf.f < tmpd.d && FPSCR_RM == 1)
dstf.l -= 1; // round toward zero
if (FPSCR & ENABLE_I)
fpu_exception_trap ();
else
FR[n] = dstf.f;
}
Possible Exceptions
FPU Error
Invalid Operation
Inexact
fcmp/eq FRm,FRn
If FRn
1111 nnnn mmmm 0100 Result
FE FE 1 1 1 1 1 1 2 1 2/4 1
F loating-point C omp areArithmetically compares the two single-precision floating-point numbers in FRn
and FRm, and stores 1 in the T bit if they are equal, or 0 otherwise.
Operation result special cases
Note
Special Cases:
When FPSCR .DN is 1, a positive denormalized number is treated as +0 and a
negative denormalized number as -0. This flush-to-zero treatment is applied before
exception detection and special case handling.
Operation
void FCMP_EQ (int m, int n)
{
PC += 2;
clear_cause ();
if (fcmp_chk_single (m, n) == INVALID)
fcmp_invalid ();
else if (fcmp_chk_single (m, n) == EQ)
T = 1;
else
T = 0;
}
int fcmp_chk_single (int m, int n)
{
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
return INVALID;
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
return UO;
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PINF:
return GT;
case NINF:
return LT;
default:
break;
}
break;
case PZERO:
case NZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
return EQ;
default:
break;
}
break;
case PINF:
switch (data_type_of (n))
{
case PINF:
return EQ;
default:
return LT;
}
case NINF:
switch (data_type_of (n))
{
case NINF:
return EQ;
default:
return GT;
}
}
if (FR[n] == FR[m])
return EQ;
else if (FR[n] > FR[m])
return GT;
else
return LT;
}
void fcmp_invalid (void)
{
set_V ();
if ((FPSCR & ENABLE_V) == 0)
T = 0;
else
fpu_exception_trap ();
}
fcmp/gt FRm,FRn
If FRn
1111 nnnn mmmm 0101 Result
FE FE 1 1 1 1 1 1 2 1 2/4 1
F loating-point C omp areArithmetically compares the two single-precision floating-point numbers in FRn
and FRm, and stores 1 in the T bit if FRn > FRm, or 0 otherwise.
Operation result special cases
Note
For IEEE 754 conform less-than-or-equal comparison it is not sufficient to swap
the operands. The FCMP/EQ must be used as well.
Operation
void FCMP_GT (int m, int n)
{
PC += 2;
clear_cause ();
if (fcmp_chk_single (m, n) == INVALID || fcmp_chk_single (m, n) == UO)
fcmp_invalid ();
else if (fcmp_chk_single (m, n) == GT)
T = 1;
else
T = 0;
}
int fcmp_chk_single (int m, int n)
{
// see description of FCMP/EQ instruction.
}
void fcmp_invalid (void)
{
// see description of FCMP/EQ instruction.
}
Possible Exceptions
Invalid operation
float FPUL,FRn
(float)FPUL
1111 nnnn 00101101 FE FE 1 1 1 1 1 1 3 1 3/4 1
Float ing-point Convert from IntegerTaking the contents of FPUL as a 32-bit integer, converts this integer to a
single-precision floating-point number and stores the result in FRn.
FPSCR .enable.I = 1 an FPU exception trap is generated regardless of whether
or not an exception has occurred. When an exception occurs, correct exception
information is reflected in FPSCR .cause and FPSCR .flag, and FRn is not updated.
Appropriate processing should therefore be performed by software.
Note
SH2E and SH3E support only invalid operation (V ) and division by zero
(Z ) exception flags.
Operation
void FLOAT_single (int n)
{
union
{
double d;
int l[2];
} tmp;
PC += 2;
clear_cause ();
FR[n] = FPUL; // convert from integer to float
tmp.d = FPUL;
if (tmp.l[1] & 0x1FFFFFFF)
inexact();
}
Possible Exceptions
Inexact
ftrc FRm,FPUL
(long)FRm
1111 mmmm 00111101 FE FE 1 1 1 1 1 1 3 1 3/4 1
F loating-point Tr uncate and C onvert to IntegerConverts the single-precision floating-point number in FRm to a 32-bit integer,
and stores the result in FPUL .
Operation result special cases
Note
The rounding mode is always truncation.
The original SH4 has a pipeline exception. If the FTRC instruction is followed
by an STS FPUL , Rn instruction, the latency of the FTRC instruction is reduced
to 1 cycle.
Operation
#define NEG_INT_SINGLE_RANGE 0xCF000000 & 0x7FFFFFFF // -1.000000 * 2^31
#define POS_INT_SINGLE_RANGE 0x4EFFFFFF // 1.FFFFFE * 2^30
void FTRC_single (int m)
{
PC += 2;
clear_cause ();
switch (ftrc_single_type_of (m))
{
case NORM:
FPUL = FR[m]; // Convert float to integer
break;
case PINF:
ftrc_invalid (0, &FPUL);
break;
case NINF:
ftrc_invalid (1, &FPUL);
break;
}
}
int ftrc_single_type_of (int m)
{
if (sign_of (m) == 0)
{
if (FR_HEX[m] > 0x7F800000)
return NINF; // NaN
else if (FR_HEX[m] > POS_INT_SINGLE_RANGE)
return PINF; // out of range, +INF
else
return NORM; // +0, +NORM
}
else
{
if ((FR_HEX[m] & 0x7FFFFFFF) > NEG_INT_SINGLE_RANGE)
return NINF; // out of range, +INF, NaN
else
return NORM; // -0, -NORM
}
}
void ftrc_invalid (int sign, int* result)
{
set_V ();
if ((FPSCR & ENABLE_V) == 0)
{
if (sign == 0)
*result = 0x7FFFFFFF;
else
*result = 0x80000000;
}
else
fpu_exception_trap ();
}
Possible Exceptions
Invalid operation
fipr FVm,FVn
inner_product (FVm, FVn)
1111 nn mm 11101101 FE FE 1 1 4/5 1
F loating-point I nner Pr oductCalculates the inner products of the 4-dimensional single-precision
floating-point vector indicated by FVn and FVm, and stores the results in
FR[n + 3].
Multiplies all terms. The results are 28 bits long.
Aligns these results, rounding them to fit within 30 bits.
Adds the aligned values.
Performs normalization and rounding.
Special processing is performed in the following cases:
If an input value is an sNaN , an invalid exception is generated.
If the input values to be multiplied include a combination of 0 and
infinity, an invalid exception is generated.
In cases other than the above, if the input values include a qNaN , the
result will be a qNaN .
In cases other than the above, if the input values include infinity:
If multiplication results in two or more infinities and the signs are
different, an invalid exception will be generated.
Otherwise, correct infinities will be stored.
If the input values do not include an sNaN , qNaN , or infinity, processing
is performed in the normal way.
When FPSCR .enable.U/I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag, and FR[n+3] is not updated. Appropriate
processing should therefore be performed by software.
Note
FV0 = { FR0 , FR1 , FR2 , FR3 }FV4 = { FR4 , FR5 , FR6 , FR7 }FV8 = { FR8 , FR9 , FR10 , FR11 }FV12 = { FR12 , FR13 , FR14 , FR15 }Operation
void FIPR (int m, int n)
{
if (FPSCR_PR == 0)
{
PC += 2;
clear_cause ();
fipr (m,n);
}
else
undefined_operation ();
}
Possible Exceptions
Invalid operation
Overflow
Generation of overflow exception traps
At least one of the following results is not less than 0xFC
(exponent of FRn) + (exponent of FRm)
(exponent of FR(n + 1)) + (exponent of FR(m + 1))
(exponent of FR(n + 2)) + (exponent of FR(m + 2))
(exponent of FR(n + 3)) + (exponent of FR(m + 3))
Underflow
Inexact
ftrv XMTRX,FVn
transform_vector (XMTRX, FVn)
1111 nn 0111111101 FE FE 1 1 5/8 4
F loating-point Tr ansform V ectorTakes the contents of floating-point registers XF0 to XF15 indicated by XMTRX
as a 4-row × 4-column matrix, takes the contents of floating-point
registers FR[n] to FR[n + 3] indicated by FVn as a 4-dimensional vector,
multiplies the array by the vector, and stores the results in FV[n].
Multiplies all terms. The results are 28 bits long.
Aligns these results, rounding them to fit within 30 bits.
Adds the aligned values.
Performs normalization and rounding.
Special processing is performed in the following cases:
If an input value is an sNaN , an invalid exception is generated.
If the input values to be multiplied include a combination of 0 and
infinity, an invalid operation exception is generated.
In cases other than the above, if the input values include a qNaN , the
result will be a qNaN .
In cases other than the above, if the input values include infinity:
If multiplication results in two or more infinities and the signs are
different, an invalid exception will be generated.
Otherwise, correct infinities will be stored.
If the input values do not include an sNaN , qNaN , or infinity, processing
is performed in the normal way.
When FPSCR .enable.V /O/U/I is set, an FPU exception trap is generated regardless
of whether or not an exception has occurred. When an exception occurs, correct
exception information is reflected in FPSCR .cause and FPSCR .flag, and FVn is not
updated. Appropriate processing should therefore be performed by software.
Note
A 4-dimensional matrix × matrix transformation can be realized by four FTRV
instructions, where every FTRV calculates a column of the result matrix. The
resulting matrix can be set to the XMTRX registers by toggling the FPSCR .FR bit
to switch register banks without copying them.
Operation
void FTRV (int n)
{
if (FPSCR_PR != 0)
undefined_operation ();
else
{
float saved_vec[4];
float result_vec[4];
int saved_fpscr;
int dst;
PC += 2;
clear_cause ();
saved_fpscr = FPSCR;
FPSCR &= ~ENABLE_VOUI; // mask VOUI enable
dst = 12 - n; // select other vector than FVn
for (int i = 0; i < 4; i++)
saved_vec[i] = FR[dst+i];
for (int i = 0; i < 4; i++)
{
for (int j = 0; j < 4; j++)
FR[dst+j] = XF[i+4j];
fipr (n, dst);
saved_fpscr |= FPSCR & (CAUSE | FLAG);
result_vec[i] = FR[dst+3];
}
for (int i = 0; i < 4; i++)
FR[dst+i] = saved_vec[i];
FPSCR = saved_fpscr;
if (FPSCR & ENABLE_VOUI)
fpu_exception_trap();
else
for (int i = 0; i < 4; i++)
FR[n+i] = result_vec[i];
}
}
Possible Exceptions
Invalid operation
Overflow
Underflow
Inexact
fsrra FRn
1.0
1111 nnnn 01111101 FE 1 1
Floating-point S quar e R eciprocal A pproximate
Takes the approximate inverse of the arithmetic square root (absolute error is
within ±2-21 ) of the single-precision floating-point in FRn
and writes the result to FRn. Since the this instruction operates by
approximation, an imprecision exception is required when the input is a
normalized value. In other cases, the instruction does not require an
imprecision exception.
FPSCR .enable.I is set, an FPU exception trap is generated. When an
exception occurs, correct exception information is reflected in FPSCR .cause and
FPSCR .flag, and FRn is not updated. Appropriate processing should therefore be
performed by software.
Operation result special cases
Note
This instruction is also supported by the SH4 variant SH7091. Other SH4
variants such as SH7751, SH7760, SH7761 might also support it.
Operation
void FSRRA (int n)
{
if (FPSCR_PR != 0)
undefined_operation ();
else
{
PC += 2;
clear_cause();
switch (data_type_of (n))
{
case NORM:
if (sign_of (n) == 0)
{
set_I ();
FR[n] = 1 / sqrt (FR[n]);
}
else
invalid (n);
break;
case DENORM:
if (sign_of (n) == 0)
fpu_error ();
else
invalid (n);
break;
case PZERO:
case NZERO:
dz (n, sign_of (n));
break;
case PINF:
FR[n] = 0;
break;
case NINF:
invalid (n);
break;
case qNAN:
qnan (n);
break;
case sNAN:
invalid (n);
break;
}
}
}
Possible Exceptions
FPU error
Invalid operation
Division by zero
Inexact
fsca FPUL,DRn
sine (FPUL)
1111 nnn 011111101 FE 1 3
F loating-point S ine And C osine A pproximateCalculates the sine and cosine approximations of FPUL (absolute error is
within ±2-21 ) as single-precision floating point values, and
places the values of the sine and cosine in FRn and FR[n + 1], respectively.
Since this instruction is an approximate operation instruction, an imprecision
exception is always required (even if the input is a 0, the result is
imprecise).
15 −360 ÷ 216 to 360 ÷ 216 degrees
16 to −360 × 215 degrees
Note
This instruction is also supported by the SH4 variant SH7091. Other SH4
variants such as SH7751, SH7760, SH7761 might also support it.
Operation
void FSCA (int n)
{
if (FPSCR_PR != 0)
undefined_operation ();
else
{
float angle;
long offset = 0x00010000;
long fraction = 0x0000FFFF;
set_I ();
fraction &= FPUL; // extract sub-rotation (fraction) part
angle = fraction; // convert to float
angle = 2 * M_PI * angle / offset; // convert to radian
FR[n] = sin (angle);
FR[n+1] = cos (angle);
PC += 2;
}
}
Possible Exceptions
Inexact
Floating-Point Double-Precision Instructions (FPSCR.PR = 1)
fabs DRn
DRn
1111 nnn 001011101 LS LS 1 1 1 0 0 1
F loating-point Abs olute ValueClears the most significant bit of the contents of floating-point register DRn
to 0, and stores the result in DRn.
Note
The cause and flag fields in FPSCR are not updated.
PR setting before this instruction.
Operation
void FABS (int n)
{
FR[n] = FR[n] & 0x7FFFFFFFF;
PC += 2;
}
fneg DRn
DRn
1111 nnn 001001101 LS LS 1 1 1 0 0 1
F loating-point Neg ate ValueInverts the most significant bit (sign bit) of the contents of floating-point
register DRn, and stores the result in DRn.
Note
The cause and flag fields in FPSCR are not updated.
PR setting before this instruction.
Operation
void FNEG (int n)
{
FR[n] = -FR[n];
PC += 2;
}
fadd DRm,DRn
DRn
1111 nnn 0 mmm 00000 FE FE 1 1 1 0/8 7/9 1
F loating-point Add Arithmetically adds the two double-precision floating-point numbers in DRn and
DRm, and stores the result in DRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and DRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Operation
void FADD (int m, int n)
{
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case NORM:
normal_faddsub (m, n, ADD);
break;
case PZERO:
case NZERO:
register_copy (m, n);
break;
default:
break;
}
break;
case PZERO:
switch (data_type_of (n))
{
case NZERO:
zero (n, 0);
break;
default:
break;
}
break;
case NZERO:
break;
case PINF:
switch (data_type_of (n))
{
case NINF:
invalid (n);
break;
default:
inf (n, 0);
break;
}
break;
case NINF:
switch (data_type_of (n))
{
case PINF:
invalid (n);
break;
default:
inf (n, 1);
break;
}
break;
}
}
Possible Exceptions
FPU Error
Invalid Operation
Overflow
Generation of overflow-exception traps
DRn and DRm have the same sign and the exponent of at least one value is 0x7FE
Underflow
Generation of underflow-exception traps
DRn and DRm have different signs and neither has an exponent greater than 0x035
Inexact
fsub DRm,DRn
DRn
1111 nnn 0 mmm 00001 FE FE 1 1 1 0/8 7/9 1
F loating-point Sub tractArithmetically subtracts the double-precision floating-point number in DRm from
the double-precision floating-point number in DRn, and stores the result in DRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and DRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Operation
void FSUB (int m, int n)
{
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case NORM:
normal_faddsub (m, n, SUB);
break;
case PZERO:
case NZERO:
register_copy (m, n);
FR[n] = -FR[n];
break;
default:
break;
}
break;
case PZERO:
break;
case NZERO:
switch (data_type_of (n))
{
case NZERO:
zero (n, 0);
break;
default:
break;
}
break;
case PINF:
switch (data_type_of (n))
{
case PINF:
invalid (n);
break;
default:
inf (n, 1);
break;
}
break;
case NINF:
switch (data_type_of (n))
{
case NINF:
invalid (n);
break;
default:
inf (n, 0);
break;
}
break;
}
}
Possible Exceptions
FPU Error
Invalid Operation
Overflow
Generation of overflow-exception traps
DRn and DRm have the same sign and the exponent of at least one value is 0x7FE
Underflow
Generation of underflow-exception traps
DRn and DRm have different signs and neither has an exponent greater than 0x035
Inexact
fmul DRm,DRn
DRn
1111 nnn 0 mmm 00010 FE FE 1 1 1 0/8 7/9 3
F loating-point Mul tiplyArithmetically multiplies the two double-precision floating-point numbers in
DRn and DRm, and stores the result in FRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and DRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Operation
void FMUL (int m, int n)
{
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else if (data_type_of (m) == DENORM || data_type_of (n) == DENORM)
set_E ();
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
default:
normal_fmul (m, n);
break;
}
break;
case PZERO:
case NZERO:
switch (data_type_of (n))
{
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n,sign_of (m) ^ sign_of (n));
break;
}
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
default:
inf (n, sign_of (m) ^ sign_of (n));
break
}
break;
}
}
Possible Exceptions
FPU Error
Invalid Operation
Overflow
Generation of overflow-exception traps
(exponent of DRn) + (exponent of DRm) - 0x3FF is not less than 0x7FE
Underflow
Generation of underflow-exception traps
(exponent of DRn) + (exponent of DRm) - 0x3FF is not more than 0x000
Inexact
fdiv DRm,DRn
DRn
1111 nnn 0 mmm 00011 FE FE 1 1 1 0/24 24/26 14
F loating-point Div ideArithmetically divides the double-precision floating-point number in DRn by the
double-precision floating-point number in DRm, and stores the result in DRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag and DRn is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Operation
void FDIV (int m, int n)
{
PC += 2;
clear_cause ();
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
invalid (n);
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
qnan (n);
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PINF:
case NINF:
inf (n, sign_of (m) ^ sign_of (n));
break;
case PZERO:
case NZERO:
zero (n, sign_of (m) ^ sign_of (n));
break;
case DENORM:
set_E ();
break;
default:
normal_fdiv_double (m, n);
break;
}
break;
case PZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
case NINF:
break;
default:
dz (n, sign_of (m) ^ sign_of (n));
break;
}
break;
case NZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
invalid (n);
break;
case PINF:
inf (n, 1);
break;
case NINF:
inf (n, 0);
break;
default:
dz (FR[n], sign_of (m) ^ sign_of (n));
break;
}
break;
case DENORM:
set_E ();
break;
case PINF:
case NINF:
switch (data_type_of (n))
{
case DENORM:
set_E ();
break;
case PINF:
case NINF:
invalid (n);
break;
default:
zero (n, sign_of (m) ^ sign_of (n));
break;
}
break;
}
}
void normal_fdiv_double (int m, int n)
{
union
{
double d;
int l[2];
} dstd, tmpd;
union
{
int double x;
int l[4];
} tmpx;
tmpd.d = DR[n >> 1]; // save destination value
dstd.d /= DR[m >> 1]; // round toward nearest or even
tmpx.x = dstd.d; // convert double to int double
tmpx.x *= DR[m >> 1];
if (tmpd.d != tmpx.x)
set_I ();
if (tmpd.d < tmpx.x && FPSCR_RM == 1)
{
dstd.l[1] -= 1; // round toward zero
if (dstd.l[1] == 0xFFFFFFFF)
dstd.l[0] -= 1;
}
check_double_exception (&DR[n >> 1], dstd.d);
}
Possible Exceptions
FPU Error
Invalid Operation
Division by zero
Overflow
Generation of overflow-exception traps
(exponent of DRn) - (exponent of DRm) + 0x3FF is not less than 0x7FF
Underflow
Generation of underflow-exception traps
(exponent of DRn) - (exponent of DRm) + 0x3FF is not more than 0x001
Inexact
fsqrt DRn
DRn 1111 nnn 001101101 FE FE 1 1 1 0/24 23/25 30
F loating-point Sq uare R oot Finds the arithmetical square root of the double-precision floating-point number
in DRn, and stores the result in DRn.
FPSCR .enable.I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When an exception occurs, correct
exception information is reflected in FPSCR .cause and FPSCR .flag and DRn is not
updated. Appropriate processing should therefore be performed by software.
Operation result special cases
Operation
void FSQRT (int n)
{
PC += 2;
clear_cause ();
switch (data_type_of (n))
{
case NORM:
if (sign_of (n) == 0)
normal_fsqrt_double (n);
else
invalid (n);
break;
case DENORM:
if (sign_of (n) == 0)
set_E ();
else
invalid (n);
break;
case PZERO:
case NZERO:
case PINF:
break;
case NINF:
invalid (n);
break;
case qNAN:
qnan (n);
break;
case sNAN:
invalid (n);
break;
}
}
void normal_fsqrt_double (int n)
{
union
{
double d;
int l[2];
} dstd, tmpd;
union
{
int double x;
int l[4];
} tmpx;
tmpd.d = DR[n >> 1]; // save destination value
dstd.d = sqrt (DR[n >> 1]); // round toward nearest or even
tmpx.x = dstd.d; // convert double to int double
tmpx.x *= dstd.d;
if (tmpd.d != tmpx.x)
set_I ();
if (tmpd.d < tmpx.x && FPSCR_RM == 1)
{
dstd.l[1] -= 1; // round toward zero
if (dstd.l[1] == 0xFFFFFFFF)
dstd.l[0] -= 1;
}
if (FPSCR & ENABLE_I)
fpu_exception_trap();
else
DR[n >> 1] = dstd.d;
}
Possible Exceptions
FPU Error
Invalid Operation
Inexact
fcmp/eq DRm,DRn
If DRn
1111 nnn 0 mmm 00100 Result
CO FE 2 2 1 3 3/5 1
F loating-point C omp areArithmetically compares the two double-precision floating-point numbers in DRn
and DRm, and stores 1 in the T bit if they are equal, or 0 otherwise.
Operation result special cases
Operation
void FCMP_EQ (int m, int n)
{
PC += 2;
clear_cause ();
if (fcmp_chk_double (m, n) == INVALID)
fcmp_invalid ();
else if (fcmp_chk_double (m, n) == EQ)
T = 1;
else
T = 0;
}
int fcmp_chk_double (int m, int n)
{
if (data_type_of (m) == sNaN || data_type_of (n) == sNaN)
return INVALID;
else if (data_type_of (m) == qNaN || data_type_of (n) == qNaN)
return UO;
else
switch (data_type_of (m))
{
case NORM:
switch (data_type_of (n))
{
case PINF:
return GT;
case NINF:
return LT;
default:
break;
}
break;
case PZERO:
case NZERO:
switch (data_type_of (n))
{
case PZERO:
case NZERO:
return EQ;
default:
break;
}
break;
case PINF:
switch (data_type_of (n))
{
case PINF:
return EQ;
default:
return LT;
}
case NINF:
switch (data_type_of (n))
{
case NINF:
return EQ;
default:
return GT;
}
}
if (DR[n >> 1] == DR[m >> 1])
return EQ;
else if (DR[n >> 1] > DR[m >> 1])
return GT;
else
return LT;
}
void fcmp_invalid (void)
{
set_V ();
if ((FPSCR & ENABLE_V) == 0)
T = 0;
else
fpu_exception_trap ();
}
Possible Exceptions
Invalid operation
fcmp/gt DRm,DRn
If DRn
1111 nnn 0 mmm 00101 Result
CO FE 2 2 1 3 3/5 1
F loating-point C omp areArithmetically compares the two double-precision floating-point numbers in DRn
and DRm, and stores 1 in the T bit if DRn > DRm, or 0 otherwise.
Operation result special cases
Note
For IEEE 754 conform less-than-or-equal comparison it is not sufficient to swap
the operands. The FCMP/EQ must be used as well.
Operation
void FCMP_GT (int m, int n)
{
PC += 2;
clear_cause ();
if (fcmp_chk_double (m, n) == INVALID || fcmp_chk_double (m, n) == UO)
fcmp_invalid ();
else if (fcmp_chk_double (m, n) == GT)
T = 1;
else
T = 0;
}
int fcmp_chk_double (int m, int n)
{
// see description of FCMP/EQ instruction.
}
void fcmp_invalid (void)
{
// see description of FCMP/EQ instruction.
}
Possible Exceptions
Invalid operation
float FPUL,DRn
(double)FPUL
1111 nnn 000101101 FE FE 1 1 1 0/4 3/5 1
Float ing-point Convert from IntegerTaking the contents of FPUL as a 32-bit integer, converts this integer to a
double-precision floating-point number and stores the result in DRn.
Operation
void FLOAT_double (int n)
{
union
{
double d;
int l[2];
} tmp;
PC += 2;
clear_cause ();
DR[n >> 1] = FPUL; // convert from integer to double
}
ftrc DRm,FPUL
(long)DRm
1111 mmm 000111101 FE FE 1 1 1 0/4 4/5 1
F loating-point Tr uncate and C onvert to IntegerConverts the double-precision floating-point number in DRm to a 32-bit integer,
and stores the result in FPUL .
Operation result special cases
Note
The rounding mode is always truncation.
Operation
#define NEG_INT_DOUBLE_RANGE 0xC1E0000000200000 & 0x7FFFFFFFFFFFFFFF
#define POS_INT_DOUBLE_RANGE 0x41E0000000000000
void FTRC_double (int m)
{
PC += 2;
clear_cause ();
switch (ftrc_double_type_of (m))
{
case NORM:
FPUL = DR[m >> 1]; // Convert double to integer
break;
case PINF:
ftrc_invalid (0, &FPUL);
break;
case NINF:
ftrc_invalid (1, &FPUL);
break;
}
}
int ftrc_double_type_of (int m)
{
if (sign_of (m) == 0)
{
if (FR_HEX[m] > 0x7FF00000
|| (FR_HEX[m] == 0x7FF00000 && FR_HEX[m+1] != 0x00000000))
return NINF; // NaN
else if (DR_HEX[m >> 1] >= POS_INT_DOUBLE_RANGE)
return PINF; // out of range, +INF
else
return NORM; // +0, +NORM
}
else
{
if ((DR_HEX[m >> 1] & 0x7FFFFFFFFFFFFFFF) >= NEG_INT_DOUBLE_RANGE)
return NINF; // out of range, +INF, NaN
else
return NORM; // -0, -NORM
}
}
void ftrc_invalid (int sign, int* result)
{
set_V ();
if ((FPSCR & ENABLE_V) == 0)
{
if (sign == 0)
*result = 0x7FFFFFFF;
else
*result = 0x80000000;
}
else
fpu_exception_trap ();
}
Possible Exceptions
Invalid operation
fcnvds DRm,FPUL
double_to_float (DRm)
1111 mmm 010111101 FE FE 1 1 1 4 4/5 1
F loating-point C onv ert D ouble to S ingle PrecisionConverts the double-precision floating-point number in DRm to a single-precision
floating-point number, and stores the result in FPUL .
FPSCR .enable. I is set, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When FPSCR .enable.O/U is set, FPU
exception traps are generated on actual generation by the FPU exception source
and on the satisfaction of certain special conditions that apply to this the
instruction. When an exception occurs, correct exception information is
reflected in FPSCR .cause and FPSCR .flag, and FPUL is not updated. Appropriate
processing should therefore be performed by software.
Operation result special cases
Operation
void FCNVDS (int m)
{
if (FPSCR_PR != 1)
undefined_operation ();
else
{
PC += 2;
clear_cause ();
switch (data_type_of (m))
{
case NORM:
case PZERO:
case NZERO:
normal_fcnvds (m, &FPUL);
break;
case DENORM:
set_E ();
case PINF:
FPUL = 0x7F800000;
break;
case NINF:
FPUL = 0xFF800000;
break;
case qNaN:
FPUL = 0x7FBFFFFF;
break;
case sNaN:
set_V ();
if ((FPSCR & ENABLE_V) == 0)
FPUL = 0x7FBFFFFF;
else
fpu_exception_trap ();
break;
}
}
}
void normal_fcnvds (int m, float* result)
{
int sign;
float abs;
union
{
float f;
int l;
} dstf, tmpf;
union
{
double d;
int l[2];
} dstd;
dstd.d = DR [m >> 1];
if (dstd.l[1] & 0x1FFFFFFF))
set_I ();
if (FPSCR_RM == 1)
dstd.l[1] &= 0xE0000000; // round toward zero
dstf.f = dstd.d;
check_single_exception (result, dstf.f);
}
Possible Exceptions
FPU error
Invalid operation
Overflow
Generation of overflow exception traps
The exponent of DRn is not less than 0x47E
Underflow
Generation of underflow exception traps
The exponent of DRn is not more than 0x380
Inexact
fcnvsd FPUL,DRn
float_to_double (FPUL)
1111 nnn 010101101 FE FE 1 1 1 4 3/5 1
F loating-point C onv ert S ingle to D ouble PrecisionConverts the single-precision floating-point number in FPUL to a
double-precision floating-point number, and stores the result in DRn.
Operation result special cases
Operation
void FCNVSD (int n)
{
if (FPSCR_PR != 1)
undefined_operation ();
else
{
switch (fpul_type ())
{
case PZERO:
case NZERO:
case PINF:
case NINF:
case NORM:
DR[n >> 1] = FPUL; // convert float to double
break;
case DENORM:
set_E ();
break;
case qNaN:
qnan (n);
break;
case sNaN:
invalid (n);
break;
}
}
}
int fpul_type ()
{
int abs = FPUL & 0x7FFFFFFF;
if (abs < 0x00800000)
{
if (FPSCR_DN == 1 || abs == 0x00000000)
{
if (sign_of (FPUL) == 0)
return PZERO;
else
return NZERO;
}
else
return DENORM;
}
else if (abs < 0x7F800000)
return NORM;
else if (abs == 0x7F800000)
{
if (sign_of (FPUL) == 0)
return PINF;
else
return NINF;
}
else if (abs < 0x7FC00000)
return qNaN;
else
return sNaN;
}
Possible Exceptions
FPU error
Invalid operation
Floating-Point Control Instructions
lds Rm,FPSCR
Rm
0100 mmmm 01101010 CO LS 1 1 1 1 1 1 3 1 4 1
L oad to FPU S ystem registerLoads the source operand into FPU system register FPSCR .
Operation
void LDSFPSCR (int m)
{
#if SH2E || SH3E
FPSCR = R[m] & 0x00018C60;
#elif SH4 || SH4A || SH2A_FPU
FPSCR = R[m] & 0x003FFFFF;
#endif
PC += 2;
}
sts FPSCR,Rn
FPSCR
0000 nnnn 01101010 CO LS 1 1 1 1 1 1 2 1 3 1
St ore from FPU S ystem RegisterStores FPU system register FPSCR in the destination.
Operation
void STSFPSCR (int n)
{
#if SH2E || SH3E
R[n] = FPSCR;
#elif SH4 || SH4A || SH2A_FPU
R[n] = FPSCR & 0x003FFFFF;
#endif
PC += 2;
}
lds.l @Rm+,FPSCR
(Rm)
0100 mmmm 01100110 CO LS 1 1 1 1 1 1 3 1 3 1
L oad to FPU S ystem registerLoads the source operand into FPU system register FPSCR .
Operation
void LDSMFPSCR (int m)
{
#if SH2E || SH3E
FPSCR = Read_32 (R[m]) & 0x00018C60;
#elif SH4 || SH4A || SH2A_FPU
FPSCR = Read_32 (R[m]) & 0x003FFFFF;
#endif
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
sts.l FPSCR,@-Rn
Rn
0100 nnnn 01100010 CO LS 1 1 1 1 1 1 1 1 1/1 1
St ore from FPU S ystem RegisterStores FPU system register FPSCR in the destination.
Operation
void STSMFPSCR (int n)
{
R[n] -= 4;
#if SH2E || SH3E
Write_32 (R[n], FPSCR);
#elif SH4 || SH4A || SH2A_FPU
Write_32 (R[n], FPSCR & 0x003FFFFF);
#endif
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
lds Rm,FPUL
Rm
0100 mmmm 01011010 LS LS 1 1 1 1 1 1 1 1 1 1
L oad to FPU S ystem RegisterLoads the source operand into FPU system register FPUL .
Operation
void LDSFPUL (int m)
{
FPUL = R[m];
PC += 2;
}
sts FPUL,Rn
FPUL
0000 nnnn 01011010 LS LS 1 1 1 1 1 1 2 1 3 1
St ore from FPU S ystem RegisterStores FPU system register FPUL in the destination.
Note
The original SH4 has a pipeline exception. If the FTRC instruction is followed
by an STS FPUL , Rn instruction, the latency of the FTRC instruction is reduced
to 1 cycle.
Operation
void STSFPUL (int n)
{
R[n] = FPUL;
PC += 2;
}
lds.l @Rm+,FPUL
(Rm)
0100 mmmm 01010110 LS LS 1 1 1 1 1 1 2 1 1/2 1
Operation
void LDSMFPUL (int m)
{
FPUL = Read_32 (R[m]);
R[m] += 4;
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
sts.l FPUL,@-Rn
Rn
0100 nnnn 01010010 CO LS 1 1 1 1 1 1 2 1 1/1 1
St ore from FPU S ystem RegisterStores FPU system register FPUL in the destination.
Operation
void STSMFPUL (int n)
{
R[n] -= 4;
Write_32 (R[n], FPUL);
PC += 2;
}
Possible Exceptions
Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception
frchg
If FPSCR.PR
1111101111111101 FE FE 1 1 1/4 1
F loating-point FR -bit Ch ang eInverts the FR bit in floating-point register FPSCR . When the FR bit in FPSCR is
changed, FR0 to FR15 in FPR0_BANK0 to FPR15_BANK0 and FPR0_BANK1 to FPR15_BANK1
become XR0 to XR15, and XR0 to XR15 become FR0 to FR15 . When FPSCR .FR = 0,
FPR0_BANK0 to FPR15_BANK0 correspond to FR0 to FR15 , and FPR0_BANK1 to
FPR15_BANK1 correspond to XR0 to XR15. When FPSCR .FR = 1, FPR0_BANK1 to
FPR15_BANK1 correspond to FR0 to FR15 , and FPR0_BANK0 to FPR15_BANK0 correspond
to XR0 to XR15.
Operation
void FRCHG (void)
{
if (FPSCR_PR == 0)
{
FPSCR ^= 0x00200000; // toggle bit 21
PC += 2;
}
else
undefined_operation ();
}
fschg
If FPSCR.PR
1111001111111101 FE FE 1 1 1 1 1/4 1
F loating-point S z-bit Ch ang eInverts the SZ bit of the floating-point status register FPSCR . Changing the
value of the SZ bit in FPSCR switches the amount of data for transfer by the
FMOV instruction between one single-precision data and a pair of
single-precision data. When FPSCR .SZ = 0, an FMOV instruction transfers a
single-precision number. When FPSCR .SZ = 1, the FMOV instruction transfers a
pair of single-precision numbers.
Operation
void FSCHG (void)
{
if (FPSCR_PR == 0)
{
FPSCR ^= 0x00100000; // toggle bit 20
PC += 2;
}
else
undefined_operation ();
}
fpchg
1111011111111101 FE 1 1
F loating-point P R-bit Ch ang eInverts the PR bit of the floating-point status register FPSCR . The value of
this bit selects single-precision or double-precision operation.
Operation
void FPCHG (void)
{
FPSCR ^= 0x00080000; // toggle bit 19
PC += 2;
}
DSP Data Transfer Instructions
nopx
No operation
1111000 * 0 * 0 * 00 ** 1 1
N o Op erationNo access operation for X memory.
movx.w @Ax,Dx
(Ax)
111100 A * D * 0 * 01 ** 1 1
Mov e between X Memory and DSP RegisterTransfers the memory source operand data to the destination register operand.
The transferred data can only be word length for X memory. The word data is
loaded to the top word of the register and the bottom word is cleared with
zeros.
Note
"*" of the instruction code is MOVY instruction designation area.
Example
movx.w @r4+,X0 ! Before execution: r4=0x08010000, @r4=0x5555, X0=0x12345678
! After execution: r4=0x08010002, X0=0x55550000
movx.w @Ax+,Dx
(Ax)
111100 A * D * 0 * 10 ** 1 1
Mov e between X Memory and DSP RegisterTransfers the memory source operand data to the destination register operand.
The transferred data can only be word length for X memory. The word data is
loaded to the top word of the register and the bottom word is cleared with
zeros.
Note
"*" of the instruction code is MOVY instruction designation area.
movx.w @Ax+Ix,Dx
(Ax)
111100 A * D * 0 * 11 ** 1 1
Mov e between X Memory and DSP RegisterTransfers the memory source operand data to the destination register operand.
The transferred data can only be word length for X memory. The word data is
loaded to the top word of the register and the bottom word is cleared with
zeros.
Note
"*" of the instruction code is MOVY instruction designation area.
movx.w Da,@Ax
MSW of Da
111100 A * D * 1 * 01 ** 1 1
Mov e between X Memory and DSP RegisterTransfers the register source operand data to the destination memory operand.
The transferred data can only be word length for X memory. The source word data
is the top word of the register.
Note
"*" of the instruction code is MOVY instruction designation area.
movx.w Da,@Ax+
MSW of Da
111100 A * D * 1 * 10 ** 1 1
Mov e between X Memory and DSP RegisterTransfers the register source operand data to the destination memory operand.
The transferred data can only be word length for X memory. The source word data
is the top word of the register.
Note
"*" of the instruction code is MOVY instruction designation area.
movx.w Da,@Ax+Ix
MSW of Da
111100 A * D * 1 * 11 ** 1 1
Mov e between X Memory and DSP RegisterTransfers the register source operand data to the destination memory operand.
The transferred data can only be word length for X memory. The source word data
is the top word of the register.
Note
"*" of the instruction code is MOVY instruction designation area.
nopy
No Operation
111100 * 0 * 0 * 0 ** 00 1 1
N o Op erationNo access operation for Y memory.
movy.w @Ay,Dy
(Ay)
111100 * A * D * 0 ** 01 1 1
Mov e between Y Memory and DSP RegisterTransfers the memory source operand data to the destination register operand.
The transferred data can only be word length for Y memory. The word data is
loaded to the top word of the register and the bottom word is cleared with
zeros.
Note
"*" of the instruction code is MOVX instruction designation area.
movy.w @Ay+,Dy
(Ay)
111100 * A * D * 0 ** 10 1 1
Mov e between Y Memory and DSP RegisterTransfers the memory source operand data to the destination register operand.
The transferred data can only be word length for Y memory. The word data is
loaded to the top word of the register and the bottom word is cleared with
zeros.
Note
"*" of the instruction code is MOVX instruction designation area.
movy.w @Ay+Iy,Dy
(Ay)
111100 * A * D * 0 ** 11 1 1
Mov e between Y Memory and DSP RegisterTransfers the memory source operand data to the destination register operand.
The transferred data can only be word length for Y memory. The word data is
loaded to the top word of the register and the bottom word is cleared with
zeros.
Note
"*" of the instruction code is MOVX instruction designation area.
movy.w Da,@Ay
MSW of Da
111100 * A * D * 1 ** 01 1 1
Mov e between Y Memory and DSP RegisterTransfers the register source operand data to the destination memory operand.
The transferred data can only be word length for Y memory. The source word data
is the top word of the register.
Note
"*" of the instruction code is MOVX instruction designation area.
movy.w Da,@Ay+
MSW of Da
111100 * A * D * 1 ** 10 1 1
Mov e between Y Memory and DSP RegisterTransfers the register source operand data to the destination memory operand.
The transferred data can only be word length for Y memory. The source word data
is the top word of the register.
Note
"*" of the instruction code is MOVX instruction designation area.
movy.w Da,@Ay+Iy
MSW of Da
111100 * A * D * 1 ** 11 1 1
Mov e between Y Memory and DSP RegisterTransfers the register source operand data to the destination memory operand.
The transferred data can only be word length for Y memory. The source word data
is the top word of the register.
Note
"*" of the instruction code is MOVX instruction designation area.
movs.w @-As,Ds
As
111101 AA DDDD 0000 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
word, the word data is loaded to the top word of the register and the bottom
word is cleared with zeros. When the destination operand is a register with
guard bits, the sign is extended and stored in the guard bits.
movs.w @As,Ds
(As)
111101 AA DDDD 0100 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
word, the word data is loaded to the top word of the register and the bottom
word is cleared with zeros. When the destination operand is a register with
guard bits, the sign is extended and stored in the guard bits.
movs.w @As+,Ds
(As)
111101 AA DDDD 1000 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
word, the word data is loaded to the top word of the register and the bottom
word is cleared with zeros. When the destination operand is a register with
guard bits, the sign is extended and stored in the guard bits.
movs.w @As+Ix,Ds
(As)
111101 AA DDDD 1100 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
word, the word data is loaded to the top word of the register and the bottom
word is cleared with zeros. When the destination operand is a register with
guard bits, the sign is extended and stored in the guard bits.
movs.w Ds,@-As
As
111101 AA DDDD 0001 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
word, the top word of the register is stored as the word data.
Note
When one of the guard bit registers A0G and A1G is the source operand it is
sign extended and stored as a word.
movs.w Ds,@As
MSW of Ds
111101 AA DDDD 0101 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
word, the top word of the register is stored as the word data.
Note
When one of the guard bit registers A0G and A1G is the source operand it is
sign extended and stored as a word.
movs.w Ds,@As+
MSW of Ds
111101 AA DDDD 1001 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
word, the top word of the register is stored as the word data.
Note
When one of the guard bit registers A0G and A1G is the source operand it is
sign extended and stored as a word.
movs.w Ds,@As+Is
MSW of DS
111101 AA DDDD 1101 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
word, the top word of the register is stored as the word data.
Note
When one of the guard bit registers A0G and A1G is the source operand it is
sign extended and stored as a word.
movs.l @-As,Ds
As
111101 AA DDDD 0010 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
longword. When the destination operand is a register with guard bits, the sign
is extended and stored in the guard bits.
movs.l @As,Ds
(As)
111101 AA DDDD 0110 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
longword. When the destination operand is a register with guard bits, the sign
is extended and stored in the guard bits.
movs.l @As+,Ds
(As)
111101 AA DDDD 1010 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
longword. When the destination operand is a register with guard bits, the sign
is extended and stored in the guard bits.
movs.l @As+Is,Ds
(As)
111101 AA DDDD 1110 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
longword. When the destination operand is a register with guard bits, the sign
is extended and stored in the guard bits.
movs.l Ds,@-As
As
111101 AA DDDD 0011 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
longword.
Note
When one of the guard bit registers A0G and A1G is the source operand it is
sign extended and stored as a word.
movs.l Ds,@As
Ds
111101 AA DDDD 0111 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
longword.
Note
When one of the guard bit registers A0G and A1G is the source operand it is
sign extended and stored as a word.
movs.l Ds,@As+
Ds
111101 AA DDDD 1011 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
longword.
Note
When one of the guard bit registers A0G and A1G is the source operand it is
sign extended and stored as a word.
movs.l Ds,@As+Is
Ds
111101 AA DDDD 1111 1 1
Mov e S ingle Data between Memory and DSP RegisterTransfers the source operand data to the destination. The transferred data is a
longword.
Note
When one of the guard bit registers A0G and A1G is the source operand it is
sign extended and stored as a word.
DSP ALU Arithmetic Operation Instructions
pabs Sx,Dz
If Sx
111110 ********** 10001000 xx 00 zzzz Update
1 1
P arallel Abs oluteFinds absolute values. When the Sx operand is positive, the contents of the
operand are transferred to the Dz operand. If the value is negative, the value
of the Sx operand is subtracted from 0 and stored in the Dz operand.
DC bit of the DSR register are updated according to the specifications of
the CS bits. The N , Z , V , and GT bits of the DSR register are updated.
Operation
void pabs_sx (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC2 = X0;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x1:
DSP_ALU_SRC2 = X1;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x2:
DSP_ALU_SRC2 = A0;
DSP_ALU_SRC2G = A0G;
break;
case 0x3:
DSP_ALU_SRC2 = A1;
DSP_ALU_SRC2G = A1G;
break;
}
if (DSP_ALU_SRC2G_BIT7 == 0)
{
// positive value
DSP_ALU_DST = 0x0 + DSP_ALU_SRC2;
carry_bit = 0;
DSP_ALU_DSTG_LSB8 = 0x0 + DSP_ALU_SRC2G_LSB8 + carry_bit;
}
else
{
// negative value
DSP_ALU_DST = 0x0 - DSP_ALU_SRC2;
borrow_bit = 1;
DSP_ALU_DSTG_LSB8 = 0x0 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
}
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
if (DSP_ALU_SRC2G_BIT7 == 0)
{
#include "fixed_pt_plus_dc_bit.c"
}
else
{
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_minus_dc_bit.c"
}
}
Example
pabs X0,
! After execution: X0=0x33333333, M0=0x33333333
pabs X1,
! After execution: X1=0x22222223
pabs Sy,Dz
If Sy
111110 ********** 1010100000 yy zzzz Update
1 1
P arallel Abs oluteFinds absolute values. When the Sy operand is positive, the contents of the
operand are transferred to the Dz operand. If the value is negative, the value
of the Sy operand is subtracted from 0 and stored in the Dz operand.
DC bit of the DSR register are updated according to the specifications of
the CS bits. The N , Z , V , and GT bits of the DSR register are updated.
Operation
void pabs_sy (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
if (DSP_ALU_SRC2G_BIT7 == 0)
{
// positive value
DSP_ALU_DST = 0x0 + DSP_ALU_SRC2;
carry_bit = 0;
DSP_ALU_DSTG_LSB8 = 0x0 + DSP_ALU_SRC2G_LSB8 + carry_bit;
}
else
{
// negative value
DSP_ALU_DST = 0x0 - DSP_ALU_SRC2;
borrow_bit = 1;
DSP_ALU_DSTG_LSB8 = 0x0 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
}
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
if (DSP_ALU_SRC2G_BIT7 == 0)
{
#include "fixed_pt_plus_dc_bit.c"
}
else
{
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_minus_dc_bit.c"
}
}
padd Sx,Sy,Dz
Sx
111110 ********** 10110001 xx yy zzzz Update
1 1
Adds the contents of the Sx and Sy operands and stores the result in the Dz
operand. The DC bit of the DSR register is updated according to the
specifications for the CS bits. The N , Z , V , and GT bits of the DSR register
are also updated.
Note
The DC bit is updated depending on the state of the CS [2:0] bit immediately
before the operation.
Operation
void padd (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1: DSP_ALU_SRC2 = Y1;
break;
case 0x2: DSP_ALU_SRC2 = M0;
break;
case 0x3: DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
}
Example
padd X0,Y0,A0
! After execution: X0=0x22222222, Y0=0x33333333, A0=0x0055555555
dct padd Sx,Sy,Dz
If DC
111110 ********** 10110010 xx yy zzzz 1 1
P arallel Add ition with ConditionConditionally adds the contents of the Sx and Sy operands and stores the result
in the Dz operand. The instruction is executed of the DC bit is set to 1.
Otherwise no operation is performed.
The DC , N , Z , V , and GT bits are not updated.
Operation
void padd_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1: DSP_ALU_SRC2 = Y1;
break;
case 0x2: DSP_ALU_SRC2 = M0;
break;
case 0x3: DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG [ex2_dz_no] = DSP_ALU_DST;
if(ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7) A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no==1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf padd Sx,Sy,Dz
If DC
111110 ********** 10110011 xx yy zzzz 1 1
P arallel Add ition with ConditionConditionally adds the contents of the Sx and Sy operands and stores the result
in the Dz operand. The instruction is executed of the DC bit is set to 0.
Otherwise no operation is performed.
The DC , N , Z , V , and GT bits are not updated.
Operation
void padd_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1: DSP_ALU_SRC2 = Y1;
break;
case 0x2: DSP_ALU_SRC2 = M0;
break;
case 0x3: DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG [ex2_dz_no] = DSP_ALU_DST;
if(ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7) A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no==1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
padd Sx,Sy,Du
pmuls Se,Sf,Dg
Sx
111110 ********** 0111 ee ff xx yy gg uu Update
1 1
Adds the contents of the Sx and Sy operands and stores the result in the Du
operand. The contents of the top word of the Se and Sf operands are multiplied
as signed and the result stored in the Dg operand. These two processes are
executed simultaneously in parallel.
DC bit of the DSR register is updated according to the results of the ALU
operation and the specifications for the CS bits. The N , Z , V , and GT bits of
the DSR register are also updated according to the results of the ALU operation.
Note
Since the PMULS is fixed decimal point multiplication, the operation result is
different from that of MULS even though the source data is the same.
Operation
void padd_pmuls (void)
{
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
switch (EX2_DU)
{
case 0x0:
X0 = DSP_ALU_DST;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
case 0x1:
Y0 = DSP_ALU_DST;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
case 0x2:
A0 = DSP_ALU_DST;
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
case 0x3:
A1 = DSP_ALU_DST;
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
}
#include "fixed_pt_plus_dc_bit.c"
}
Example
padd A0,M0,A0
! Before execution: X0=0x00020000, Y0=0x00030000, M0=0x22222222, A0=0x0055555555
! After execution: X0=0x00020000, Y0=0x00030000, M0=0x0000000C, A0=0x0077777777
paddc Sx,Sy,Dz
Sx
111110 ********** 10110000 xx yy zzzz Update
1 1
P arallel Add ition with C arryAdds the contents of the Sx and Sy operands to the DC bit and stores the result
in the Dz operand. The DC bit of the DSR register is updated as the carry flag.
The N , Z , V , and GT bits of the DSR register are also updated.
Note
The DC bit is updated as the carry flag after execution of the PADDC instruction
regardless of the CS bits.
CS [2:0] = ***: Always operate as Carry or Borrow mode, regardless of the status
of the DC bit.
Operation
void paddc (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2 + DSPDCBIT;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_dc_always_carry.c"
}
Example
paddc X0,Y0,M0
! After execution: X0=0xB3333333, Y0=0x55555555 M0=0x08888888, DC=1
paddc X0,Y0,M0
! After execution: X0=0x33333333, Y0=0x55555555 M0=0x88888889, DC=0
pclr Dz
0x00000000
111110 ********** 100011010000 zzzz Update
1 1
Clears the Dz operand. The DC bit of the DSR register is updated according to
the specifications for the CS bits. The Z bit of the DSR register is set to 1.
The N , V , and GT bits are cleared to 0.
Operation
void pclr (void)
{
DSP_REG[ex2_dz_no] = 0x0;
if (ex2_dz_no == 0)
A0G = 0x0;
else if (ex2_dz_no == 1)
A1G = 0x0;
carry_bit = 0;
negative_bit = 0;
zero_bit = 1;
overflow_bit = 0;
#include "fixed_pt_plus_dc_bit.c"
}
Example
pclr A0
! After execution: A0=0x0000000000
dct pclr Dz
If DC
111110 ********** 100011100000 zzzz 1 1
P arallel Cl ear Conditionally clears the Dz operand. The instruction is executed when the DC
bit is set to 1. The DC , N , Z , V , and GT bits are not updated.
Operation
void pclr_dct (void)
{
if (DC == 1)
DSP_REG[ex2_dz_no] = 0x0;
}
dcf pclr Dz
If DC
111110 ********** 100011110000 zzzz 1 1
P arallel Cl ear Conditionally clears the Dz operand. The instruction is executed when the DC
bit is set to 0. The DC , N , Z , V , and GT bits are not updated.
Operation
void pclr_dcf (void)
{
if (DC == 0)
DSP_REG[ex2_dz_no] = 0x0;
}
pcmp Sx,Sy
Sx
111110 ********** 10000100 xx yy 0000 Update
1 1
P arallel C omp are Two DataSubtracts the contents of the Sy operand from the Sx operand. The DC bit of the
DSR register is updated according to the specifications for the CS bits.
The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void pcmp (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_minus_dc_bit.c"
}
Example
pcmp X0,
! After execution: X0=0x22222222, Y0=0x33333333 N=1, Z=0, V=0, GT=0
pcopy Sx,Dz
Sx
111110 ********** 11011001 xx 00 zzzz Update
1 1
Stores the Sx operand in the Dz operand. The DC bit of the DSR register
is updated according to the specifications for the CS bits. The N , Z , V , and GT
bits are also updated.
Operation
void pcopy_sx (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_SRC2 = 0;
DSP_ALU_SRC2G = 0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
}
pcopy Sy,Dz
Sy
111110 ********** 1111100100 yy zzzz Update
1 1
Stores the Sy operand in the Dz operand. The DC bit of the DSR register
is updated according to the specifications for the CS bits. The N , Z , V , and GT
bits are also updated.
Operation
void pcopy_sy (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
}
Example
pcopy X0,
! After execution: X0=0x55555555, A0=0x0055555555
dct pcopy Sx,Dz
If DC
111110 ********** 11011010 xx 00 zzzz 1 1
P arallel Copy with ConditionConditionally stores the Sx operand in the Dz operand. The instruction
is executed if the DC bit is set to 1. The DC , N , Z , V , and GT bits are not
updated.
Operation
void pcopy_sx_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_SRC2 = 0;
DSP_ALU_SRC2G = 0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dct pcopy Sy,Dz
If DC
111110 ********** 1111101000 yy zzzz 1 1
P arallel Copy with ConditionConditionally stores the Sy operand in the Dz operand. The instruction
is executed if the DC bit is set to 1. The DC , N , Z , V , and GT bits are not
updated.
Operation
void pcopy_sy_dct (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pcopy Sx,Dz
If DC
111110 ********** 11011011 xx 00 zzzz 1 1
P arallel Copy with ConditionConditionally stores the Sx operand in the Dz operand. The instruction
is executed if the DC bit is set to 0. The DC , N , Z , V , and GT bits are not
updated.
Operation
void pcopy_sx_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_SRC2 = 0;
DSP_ALU_SRC2G = 0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pcopy Sy,Dz
If DC
111110 ********** 1111101100 yy zzzz 1 1
P arallel Copy with ConditionConditionally stores the Sy operand in the Dz operand. The instruction
is executed if the DC bit is set to 0. The DC , N , Z , V , and GT bits are not
updated.
Operation
void pcopy_sy_dcf (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 + DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
pneg Sx,Dz
0
111110 ********** 11001001 xx 00 zzzz Update
1 1
Reverses the sign. Subtracts the Sx operand from 0 and stores the result in
the Dz operand. The DC bit of the DSR register is updated according to the
specifications for the CS bits. The N , Z , V , and GT bits of the DSR register
are also updated.
Operation
void pneg_sx (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC2 = X0;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x1:
DSP_ALU_SRC2 = X1;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x2:
DSP_ALU_SRC2 = A0;
DSP_ALU_SRC2G = A0G;
break;
case 0x3:
DSP_ALU_SRC2 = A1;
DSP_ALU_SRC2G = A1G;
break;
}
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_minus_dc_bit.c"
}
Example
pneg X0,A0
! After execution: X0=0x55555555, A0=0xFFAAAAAAAB
pneg X1,Y1
! After execution: Y1=0x66666667
pneg Sy,Dz
0
111110 ********** 1110100100 yy zzzz Update
1 1
Reverses the sign. Subtracts the Sy operand from 0 and stores the result in
the Dz operand. The DC bit of the DSR register is updated according to the
specifications for the CS bits. The N , Z , V , and GT bits of the DSR register
are also updated.
Operation
void pneg_sy (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_minus_dc_bit.c"
}
dct pneg Sx,Dz
If DC
111110 ********** 11001010 xx 00 zzzz 1 1
P arallel Neg ateConditionally reverses the sign. The instruction is executed if the DC bit is
set to 1. Subtracts the Sx operand from 0 and stores the result in the Dz
operand. The DC , N , Z , V , and GT bits are not updated.
Operation
void pneg_sx_dct (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC2 = X0;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x1:
DSP_ALU_SRC2 = X1;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x2:
DSP_ALU_SRC2 = A0;
DSP_ALU_SRC2G = A0G;
break;
case 0x3:
DSP_ALU_SRC2 = A1;
DSP_ALU_SRC2G = A1G;
break;
}
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dct pneg Sy,Dz
If DC
111110 ********** 1110101000 yy zzzz 1 1
P arallel Neg ateConditionally reverses the sign. The instruction is executed if the DC bit is
set to 1. Subtracts the Sy operand from 0 and stores the result in the Dz
operand. The DC , N , Z , V , and GT bits are not updated.
Operation
void pneg_sy_dct (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pneg Sx,Dz
If DC
111110 ********** 11001011 xx 00 zzzz 1 1
P arallel Neg ateConditionally reverses the sign. The instruction is executed if the DC bit is
set to 0. Subtracts the Sx operand from 0 and stores the result in the Dz
operand. The DC , N , Z , V , and GT bits are not updated.
Operation
void pneg_sx_dcf (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC2 = X0;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x1:
DSP_ALU_SRC2 = X1;
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
break;
case 0x2:
DSP_ALU_SRC2 = A0;
DSP_ALU_SRC2G = A0G;
break;
case 0x3:
DSP_ALU_SRC2 = A1;
DSP_ALU_SRC2G = A1G;
break;
}
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pneg Sy,Dz
If DC
111110 ********** 1110101100 yy zzzz 1 1
P arallel Neg ateConditionally reverses the sign. The instruction is executed if the DC bit is
set to 0. Subtracts the Sy operand from 0 and stores the result in the Dz
operand. The DC , N , Z , V , and GT bits are not updated.
Operation
void pneg_sy_dcf (void)
{
DSP_ALU_SRC1 = 0;
DSP_ALU_SRC1G = 0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
psub Sx,Sy,Dz
Sx
111110 ********** 10100001 xx yy zzzz Update
1 1
Subtracts the contents of the Sy operand from the Sx operand and stores the
result in the Dz operand. The DC bit of the DSR register is updated according
to the specifications for the CS bits. The N , Z , V , and GT bits of the DSR
register are updated.
Operation
void psub (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_minus_dc_bit.c"
}
Example
psub X0,Y0,A0
! After execution: X0=0x55555555, Y0=0x33333333, A0=0x0022222222
dct psub Sx,Sy,Dz
If DC
111110 ********** 10100010 xx yy zzzz 1 1
P arallel Sub tract with ConditionConditionally subtracts the contents of the Sy operand from the Sx operand and
stores the result in the Dz operand. The instruction is executed if the DC bit
is set to 1. The DC , N , Z , V , and GT bits are not updated.
Operation
void psub_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf psub Sx,Sy,Dz
If DC
111110 ********** 10100011 xx yy zzzz 1 1
P arallel Sub tract with ConditionConditionally subtracts the contents of the Sy operand from the Sx operand and
stores the result in the Dz operand. The instruction is executed if the DC bit
is set to 0. The DC , N , Z , V , and GT bits are not updated.
Operation
void psub_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
psub Sx,Sy,Du
pmuls Se,Sf,Dg
Sx
111110 ********** 0110 ee ff xx yy gg uu Update
1 1
Subtracts the contents of the Sy operand from the Sx operand and stores the
result in the Du operand. The contents of the top word of the Se and Sf operands
are multiplied as signed and the result stored in the Dg operand. These two
processes are executed simultaneously in parallel.
DC bit of the DSR register is updated according to the results of the ALU
operation and the specifications for the CS bits. The N , Z , V , and GT bits of
the DSR register are also updated according to the results of the ALU operation.
Operation
void psub_pmuls (void)
{
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
switch (EX2_DU)
{
case 0x0:
X0 = DSP_ALU_DST;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST == 0);
break;
case 0x1:
Y0 = DSP_ALU_DST;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST == 0);
break;
case 0x2:
A0 = DSP_ALU_DST;
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
case 0x3:
A1 = DSP_ALU_DST;
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
negative_bit = DSP_ALU_DSTG_BIT7;
zero_bit = (DSP_ALU_DST == 0) & (DSP_ALU_DSTG_LSB8 == 0);
break;
}
#include "fixed_pt_minus_dc_bit.c"
}
Example
psub A0,M0,A0
! After execution: X0=0x00020000, Y0=0xFFFE0000, M0=0xFFFFFFF8, A0=0x55555555
psubc Sx,Sy,Dz
Sx − Sy
111110 ********** 10100000 xx yy zzzz Update
1 1
P arallel Sub traction with C arrySubtracts the contents of the Sy operand and the DC bit from the Sx operand and
stores the result in the Dz operand. The DC bit of the DSR register is updated
as the borrow flag. The N , Z , V , and GT bits of the DSR register are also
updated.
Operation
void psubc (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
DSP_ALU_DST = DSP_ALU_SRC1 - DSP_ALU_SRC2 - DSPDCBIT;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = MINUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_dc_always_borrow.c"
}
Example
psubc X0,Y0,M0
! After execution: X0=0x33333333, Y0=0x55555555 M0=0xFFDDDDDDDE, DC=1
psubc X0,Y0,M0
! After execution: X0=0x33333333, Y0=0x55555555 M0=0xFFDDDDDDDD, DC=1
pdec Sx,Dz
MSW of Sx
111110 ********** 10001001 xx 00 zzzz Update
1 1
Subtracts 1 from the top word of the Sx operand, stores the result in the upper
word of the Dz operand, and clears the bottom word of the Dz operand with zeros.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Note
The bottom word of the destination register is ignored when the DC bit is
updated.
Operation
void pdec_sx (void)
{
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_minus_dc_bit.c"
}
Example
pdec X0,M0
! After execution: X0=0x0052330F, M0=0x00510000
pdec X1,X1
! After execution: X1=0xFC330000
pdec Sy,Dz
MSW of Sy
111110 ********** 1010100100 yy zzzz Update
1 1
Subtracts 1 from the top word of the Sy operand, stores the result in the upper
word of the Dz operand, and clears the bottom word of the Dz operand with zeros.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Note
The bottom word of the destination register is ignored when the DC bit is
updated.
Operation
void pdec_sy (void)
{
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_minus_dc_bit.c"
}
dct pdec Sx,Dz
If DC
111110 ********** 10001010 xx 00 zzzz 1 1
P arallel Dec rement by 1Conditionally subtracts 1 from the top word of the Sx operand, stores the result
in the upper word of the Dz operand, and clears the bottom word of the Dz
operand with zeros. The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pdec_sx_dct (void)
{
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dct pdec Sy,Dz
If DC
111110 ********** 1010101000 yy zzzz 1 1
P arallel Dec rement by 1Conditionally subtracts 1 from the top word of the Sy operand, stores the result
in the upper word of the Dz operand, and clears the bottom word of the Dz
operand with zeros. The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pdec_sy_dct (void)
{
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pdec Sx,Dz
If DC
111110 ********** 10001011 xx 00 zzzz 1 1
P arallel Dec rement by 1Conditionally subtracts 1 from the top word of the Sx operand, stores the result
in the upper word of the Dz operand, and clears the bottom word of the Dz
operand with zeros. The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pdec_sx_dcf (void)
{
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pdec Sy,Dz
If DC
111110 ********** 1010101100 yy zzzz 1 1
P arallel Dec rement by 1Conditionally subtracts 1 from the top word of the Sy operand, stores the result
in the upper word of the Dz operand, and clears the bottom word of the Dz
operand with zeros. The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pdec_sy_dcf (void)
{
DSP_ALU_SRC2 = 0x1;
DSP_ALU_SRC2G = 0x0;
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW - 1;
carry_bit = ((DSP_ALU_SRC1_MSB | ! DSP_ALU_SRC2_MSB) && ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & ! DSP_ALU_SRC2_MSB);
borrow_bit = ! carry_bit;
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 - DSP_ALU_SRC2G_LSB8 - borrow_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
pinc Sx,Dz
MSW of Sy
111110 ********** 10011001 xx 00 zzzz Update
1 1
Adds 1 to the top word of the Sx operand, stores the result in the upper word
of the Dz operand, and clears the bottom word of the Dz operand with zeros.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void pinc_sx (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
}
Example
pinc X0,M0
! After execution: X0=0x0052330F, M0=0x00530000
pinc X1,X1
! After execution: X1=0xFC350000
pinc Sy,Dz
MSW of Sy
111110 ********** 1011100100 yy zzzz Update
1 1
Adds 1 to the top word of the Sy operand, stores the result in the upper word
of the Dz operand, and clears the bottom word of the Dz operand with zeros.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void pinc_sy (void)
{
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
}
dct pinc Sx,Dz
If DC
111110 ********** 10011010 xx 00 zzzz 1 1
P arallel Inc rement by 1 with ConditionConditionally adds 1 to the top word of the Sx operand, stores the result in the
upper word of the Dz operand, and clears the bottom word of the Dz operand with
zeros. The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pinc_sx_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dct pinc Sy,Dz
If DC
111110 ********** 1011101000 yy zzzz 1 1
P arallel Inc rement by 1 with ConditionConditionally adds 1 to the top word of the Sy operand, stores the result in the
upper word of the Dz operand, and clears the bottom word of the Dz operand with
zeros. The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pinc_sy_dct (void)
{
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pinc Sx,Dz
If DC
111110 ********** 10011011 xx 00 zzzz 1 1
P arallel Inc rement by 1 with ConditionConditionally adds 1 to the top word of the Sx operand, stores the result in the
upper word of the Dz operand, and clears the bottom word of the Dz operand with
zeros. The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pinc_sx_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pinc Sy,Dz
If DC
111110 ********** 1011101100 yy zzzz 1 1
P arallel Inc rement by 1 with ConditionConditionally adds 1 to the top word of the Sy operand, stores the result in the
upper word of the Dz operand, and clears the bottom word of the Dz operand with
zeros. The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pinc_sy_dcf (void)
{
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW + 1;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "integer_overflow_protection.c"
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
pdmsb Sx,Dz
Sx data MSB position
111110 ********** 10011101 xx 00 zzzz Update
1 1
Finds the first position to change in the lineup of Sx operand bits and stores
the bit position in the Dz operand. The DC bit of the DSR register is updated
according to the specifications for the CS bits. The N , Z , V , and GT bits of the
DSR register are also updated.
Operation
void pdmsb_sx (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
overflow_bit = 0;
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
}
Example
pdmsb X0,M0
! After execution: X0=0x0052330F, M0=0x00080000
pdmsb X1,X1
! After execution: X1=0x00050000
pdmsb Sy,Dz
Sy data MSB position
111110 ********** 1011110100 yy zzzz Update
1 1
Finds the first position to change in the lineup of Sy operand bits and stores
the bit position in the Dz operand. The DC bit of the DSR register is updated
according to the specifications for the CS bits. The N , Z , V , and GT bits of the
DSR register are also updated.
Operation
void pdmsb_sy (void)
{
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
overflow_bit = 0;
#include "integer_unconditional_update.c"
#include "integer_plus_dc_bit.c"
}
dct pdmsb Sx,Dz
If DC
111110 ********** 10011110 xx 00 zzzz 1 1
P arallel D etect M ost S ignificant B it with ConditionConditionally finds the first position to change in the lineup of Sx operand
bits and stores the bit position in the Dz operand. The instruction is executed
if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pdmsb_sx_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dct pdmsb Sy,Dz
If DC
111110 ********** 1011111000 yy zzzz 1 1
P arallel D etect M ost S ignificant B it with ConditionConditionally finds the first position to change in the lineup of Sy operand
bits and stores the bit position in the Dz operand. The instruction is executed
if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pdmsb_sy_dct (void)
{
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pdmsb Sx,Dz
If DC
111110 ********** 10011111 xx 00 zzzz 1 1
P arallel D etect M ost S ignificant B it with ConditionConditionally finds the first position to change in the lineup of Sx operand
bits and stores the bit position in the Dz operand. The instruction is executed
if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pdmsb_sx_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf pdmsb Sy,Dz
If DC
111110 ********** 1011111100 yy zzzz 1 1
P arallel D etect M ost S ignificant B it with ConditionConditionally finds the first position to change in the lineup of Sy operand
bits and stores the bit position in the Dz operand. The instruction is executed
if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pdmsb_sy_dcf (void)
{
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
short int i;
unsigned char msb, src1g;
unsigned long src1 = DSP_ALU_SRC1;
msb = DSP_ALU_SRC1G_BIT7;
src1g = (DSP_ALU_SRC1G_LSB8 << 1);
for (i = 38; ((msb == (src1g >> 7)) && (i >= 32)); i--)
src1g <<= 1;
if (i == 31)
for(i; ((msb == (src1 >> 31)) && (i >= 0)); i--)
src1 <<= 1;
DSP_ALU_DST = 0x0;
DSP_ALU_DST_HW = (short int)(30 - i);
if (DSP_ALU_DST_MSB)
DSP_ALU_DSTG_LSB8 = 0xFF;
else
DSP_ALU_DSTG_LSB8 = 0x0;
carry_bit = 0;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
prnd Sx,Dz
Sx
111110 ********** 10011000 xx 00 zzzz 1 1
P arallel R ound ingDoes rounding. Adds the immediate data 0x00008000 to the contents of the Sx
operand, stores the result in the upper word of the Dz operand, and clears the
bottom word of Dz with zeros.
DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void prnd_sx (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
DSP_ALU_DST = (DSP_ALU_SRC1 + DSP_ALU_SRC2) & MASKFFFF0000;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
}
Example
prnd X0,M0
! After execution: X0=0x0052330F, M0=0x00520000
prnd X1,X1
! After execution: X1=0xFC350000
prnd Sy,Dz
Sy
111110 ********** 1011100000 yy zzzz 1 1
P arallel R ound ingDoes rounding. Adds the immediate data 0x00008000 to the contents of the Sy
operand, stores the result in the upper word of the Dz operand, and clears the
bottom word of Dz with zeros.
DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void prnd_sy (void)
{
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC1 = Y0;
break;
case 0x1:
DSP_ALU_SRC1 = Y1;
break;
case 0x2:
DSP_ALU_SRC1 = M0;
break;
case 0x3:
DSP_ALU_SRC1 = M1;
break;
}
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
DSP_ALU_DST = (DSP_ALU_SRC1 + DSP_ALU_SRC2) & MASKFFFF0000;
carry_bit = ((DSP_ALU_SRC1_MSB | DSP_ALU_SRC2_MSB) & ! DSP_ALU_DST_MSB)
| (DSP_ALU_SRC1_MSB & DSP_ALU_SRC2_MSB);
DSP_ALU_DSTG_LSB8 = DSP_ALU_SRC1G_LSB8 + DSP_ALU_SRC2G_LSB8 + carry_bit;
overflow_bit = PLUS_OP_G_OV || ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "fixed_pt_plus_dc_bit.c"
}
DSP ALU Logical Operation Instructions
pand Sx,Sy,Dz
Sx
111110 ********** 10010101 xx yy zzzz Update
1 1
Does an AND of the upper word of the Sx operand and the upper word of the Sy
operand, stores the result in the upper word of the Dz operand, and clears the
bottom word of the Dz operand with zeros. When Dz is a register that has guard
bits, the guard bits are also zeroed. The DC bit of the DSR register is updated
according to the specifications for the CS bits. The N , Z , V , and GT bits of
the DSR register are also updated.
Note
The bottom word of the destination register and the guard bits are ignored when
the DC bit is updated.
Operation
void pand (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW & DSP_ALU_SRC2_HW;
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
carry_bit = 0x0;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST_HW == 0);
overflow_bit = 0x0;
#include "logical_dc_bit.c"
}
Example
pand X0,Y0,A0
! After execution: X0=0x33333333, Y0=0x55555555 A0=0x0011110000
dct pand Sx,Sy,Dz
If DC
111110 ********** 10010110 xx yy zzzz 1 1
P arallel Logical And Conditionally does an AND of the upper word of the Sx operand and the upper word
of the Sy operand, stores the result in the upper word of the Dz operand, and
clears the bottom word of the Dz operand with zeros. When Dz is a register that
has guard bits, the guard bits are also zeroed.
The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pand_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW & DSP_ALU_SRC2_HW;
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no==1)
A1G = 0x0;
}
}
dcf pand Sx,Sy,Dz
If DC
111110 ********** 10010111 xx yy zzzz 1 1
P arallel Logical And Conditionally does an AND of the upper word of the Sx operand and the upper word
of the Sy operand, stores the result in the upper word of the Dz operand, and
clears the bottom word of the Dz operand with zeros. When Dz is a register that
has guard bits, the guard bits are also zeroed.
The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pand_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW & DSP_ALU_SRC2_HW;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no==1)
A1G = 0x0;
}
}
por Sx,Sy,Dz
Sx
111110 ********** 10110101 xx yy zzzz Update
1 1
Takes the OR of the top word of the Sx operand and the top word of the Sy
operand, stores the result in the top word of the Dz operand, and clears the
bottom word of Dz with zeros. When Dz is a register that has guard bits, the
guard bits are also zeroed. The DC bit of the DSR register is updated
according to the specifications for the CS bits. The N , Z , V , and GT bits of
the DSR register are also updated.
Note
The bottom word of the destination register and the guard bits are ignored when
the DC bit is updated.
Operation
void por (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW | DSP_ALU_SRC2_HW;
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
carry_bit = 0x0;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST_HW == 0);
overflow_bit = 0x0;
#include "logical_dc_bit.c"
}
Example
por X0,Y0,A0
! After execution: X0=0x33333333, Y0=0x55555555 A0=0x127777789A
dct por Sx,Sy,Dz
If DC
111110 ********** 10110110 xx yy zzzz 1 1
P arallel Logical Or Conditionally takes the OR of the top word of the Sx operand and the top word
of the Sy operand, stores the result in the top word of the Dz operand, and
clears the bottom word of Dz with zeros. When Dz is a register that has guard
bits, the guard bits are also zeroed. The instruction is executed if the DC bit
is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void por_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW | DSP_ALU_SRC2_HW;
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // /* */
else if (ex2_dz_no == 1)
A1G = 0x0;
}
}
dcf por Sx,Sy,Dz
If DC
111110 ********** 10110111 xx yy zzzz 1 1
P arallel Logical Or Conditionally takes the OR of the top word of the Sx operand and the top word
of the Sy operand, stores the result in the top word of the Dz operand, and
clears the bottom word of Dz with zeros. When Dz is a register that has guard
bits, the guard bits are also zeroed. The instruction is executed if the DC bit
is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void por_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW | DSP_ALU_SRC2_HW;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // /* */
else if (ex2_dz_no == 1)
A1G = 0x0;
}
}
pxor Sx,Sy,Dz
Sx
111110 ********** 10100101 xx yy zzzz Update
1 1
Takes the exclusive OR of the top word of the Sx operand and the top word of the
Sy operand, stores the result in the top word of the Dz operand, and clears the
bottom word of Dz with zeros. When Dz is a register that has guard bits, the
guard bits are also zeroed. The DC bit of the DSR register is updated according
to the specifications for the CS bits. The N , Z , V , and GT bits of the DSR
register are also updated.
Note
The bottom word of the destination register and the guard bits are ignored when
the DC bit is updated.
Operation
void pxor (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW ^ DSP_ALU_SRC2_HW;
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
carry_bit = 0x0;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = (DSP_ALU_DST_HW == 0);
overflow_bit = 0x0;
#include "logical_dc_bit.c"
}
Example
pxor X0,Y0,A0
! After execution: X0=0x33333333, Y0=0x55555555 A0=0x0066660000
dct pxor Sx,Sy,Dz
If DC
111110 ********** 10100110 xx yy zzzz 1 1
P arallel Logical Ex clusive Or Conditionally takes the exclusive OR of the top word of the Sx operand and the
top word of the Sy operand, stores the result in the top word of the Dz operand,
and clears the bottom word of Dz with zeros. When Dz is a register that has
guard bits, the guard bits are also zeroed.
The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pxor_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW ^ DSP_ALU_SRC2_HW;
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
}
}
dcf pxor Sx,Sy,Dz
If DC
111110 ********** 10100111 xx yy zzzz 1 1
P arallel Logical Ex clusive Or Conditionally takes the exclusive OR of the top word of the Sx operand and the
top word of the Sy operand, stores the result in the top word of the Dz operand,
and clears the bottom word of Dz with zeros. When Dz is a register that has
guard bits, the guard bits are also zeroed.
The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pxor_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0;
break;
case 0x1:
DSP_ALU_SRC2 = Y1;
break;
case 0x2:
DSP_ALU_SRC2 = M0;
break;
case 0x3:
DSP_ALU_SRC2 = M1;
break;
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW ^ DSP_ALU_SRC2_HW;
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
}
}
DSP Fixed Decimal Point Multiplication Instructions
pmuls Se,Sf,Dg
MSW of Se
111110 ********** 0100 ee ff 0000 gg 00 1 1
P arallel Mul tiply S igned by SignedThe contents of the top word of the Se and Sf operands are multiplied as signed
and the result stored in the Dg operand. The DC , N , Z , V , and GT bits of the
DSR register are not updated.
Note
Since PMULS is fixed decimal point multiplication, the operation result is
different from that of MULS even though the source data is the same.
Operation
void pmuls (void)
{
switch (ee) // Se Operand selection bit (ee)
{
case 0x0:
DSP_M_SRC1 = X0;
break;
case 0x1:
DSP_M_SRC1 = X1;
break;
case 0x2:
DSP_M_SRC1 = Y0;
break;
case 0x3:
DSP_M_SRC1 = A1;
break;
}
switch (ff) // Sf Operand selection bit (ff)
{
case 0x0:
DSP_M_SRC2 = Y0;
break;
case 0x1:
DSP_M_SRC2 = Y1;
break;
case 0x2:
DSP_M_SRC2 = X0;
break;
case 0x3:
DSP_M_SRC2 = A1;
break;
}
if ((SBIT == 1) && (DSP_M_SRC1 == 0x8000) && (DSP_M_SRC2 == 0x8000))
DSP_M_DST = 0x7FFFFFFF; // overflow protection
else
DSP_M_DST= ((long)(short)DSP_M_SRC1 * (long)(short)DSP_M_SRC2) << 1;
if (DSP_M_DST_MSB)
DSP_M_DSTG_LSB8 = 0xFF;
else
DSP_M_DSTG_LSB8 = 0x0;
switch (gg) // Dg Operand selection bit (gg)
{
case 0x0:
M0 = DSP_M_DST;
break;
case 0x1:
M1 = DSP_M_DST;
break;
case 0x2:
A0 = DSP_M_DST;
if (DSP_M_DSTG_LSB8 == 0x0)
A0G=0x0;
else
A0G = 0xFFFFFFFF;
break;
case 0x3:
A1 = DSP_M_DST;
if (DSP_M_DSTG_LSB8 == 0x0)
A1G = 0x0;
else
A1G = 0xFFFFFFFF;
break;
}
}
Example
pmuls X0,Y0,M0
! After execution: X0=0x00010000, Y0=0x00020000, M0=0x00000004
pmuls X1,Y1,A0
! After execution: X1=0xFFFE2222, Y1=0x0001AAAA, A0=0xFFFFFFFFFC
DSP Shift Operation Instructions
psha Sx,Sy,Dz
If Sy
111110 ********** 10010001 xx yy zzzz Update
1 1
Arithmetically shifts the contents of the Sx or Dz operand and stores the result
in the Dz operand. The amount of the shift is specified by the Sy operand.
When the shift amount is positive, it shifts left. When the shift amount is
negative, it shifts right.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void psha (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0 & MASK007F0000;
break;
case 0x1:
DSP_ALU_SRC2 = Y1 & MASK007F0000;
break;
case 0x2:
DSP_ALU_SRC2 = M0 & MASK007F0000;
break;
case 0x3:
DSP_ALU_SRC2 = M1 & MASK007F0000;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
if ((DSP_ALU_SRC2_HW & MASK0040) == 0)
{
// Left Shift 0 <= cnt <= 32
char cnt = DSP_ALU_SRC2_HW & MASK003F;
if (cnt > 32)
{
printf ("\nPSHA Sz,Sy,Dz Error! Shift %2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST = DSP_ALU_SRC1 << cnt;
DSP_ALU_DSTG = ((DSP_ALU_SRC1G << cnt)
| (DSP_ALU_SRC1 >> (32 - cnt))) & MASK000000FF;
carry_bit = ((DSP_ALU_DSTG & MASK00000001) == 0x1);
}
else
{
// Right Shift 0 < cnt <= 32
char cnt = (~DSP_ALU_SRC2_HW & MASK003F) + 1;
if (cnt > 32)
{
printf ("\nPSHA Sz,Sy,Dz Error! shift -%2X exceed range.\n", cnt);
exit ();
}
if ((cnt > 8) && DSP_ALU_SRC1G_BIT7)
{
// MSB copy
DSP_ALU_DST = (DSP_ALU_SRC1 >> 8) | (DSP_ALU_SRC1G << (32 - 8));
DSP_ALU_DST = (long)DSP_ALU_DST >> (cnt - 8);
}
else
DSP_ALU_DST = (DSP_ALU_SRC1 >> cnt) | (DSP_ALU_SRC1G << (32 - cnt));
DSP_ALU_DSTG_LSB8 = (char)DSP_ALU_SRC1G_LSB8 >> cnt--;
carry_bit = ((DSP_ALU_SRC1 >> cnt) & MASK00000001) == 0x1;
}
overflow_bit = ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "shift_dc_bit.c"
}
Example
sha X0,Y0,A0
a0
! After execution: X0=0x88888888, Y0=0x00020000,
a0
psha X0,Y0,X0
! After execution: X0=0x19999999, Y0=0xFFFE0000
dct psha Sx,Sy,Dz
If DC
111110 ********** 10010010 xx yy zzzz 1 1
P arallel Sh ift A rithmetically with ConditionConditionally arithmetically shifts the contents of the Sx operand and
stores the result in the Dz operand. The amount of the shift is specified by
the Sy operand. When the shift amount is positive, it shifts left. When the
shift amount is negative, it shifts right.
The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void psha_dct (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0 & MASK007F0000;
break;
case 0x1:
DSP_ALU_SRC2 = Y1 & MASK007F0000;
break;
case 0x2:
DSP_ALU_SRC2 = M0 & MASK007F0000;
break;
case 0x3:
DSP_ALU_SRC2 = M1 & MASK007F0000;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
if ((DSP_ALU_SRC2_HW & MASK0040) == 0)
{
// Left Shift 0 <= cnt <= 32
char cnt = DSP_ALU_SRC2_HW & MASK003F;
if (cnt > 32)
{
printf ("\nPSHA Sz,Sy,Dz Error! Shift %2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST = DSP_ALU_SRC1 << cnt;
DSP_ALU_DSTG = ((DSP_ALU_SRC1G << cnt)
| (DSP_ALU_SRC1 >> (32 - cnt))) & MASK000000FF;
carry_bit = ((DSP_ALU_DSTG & MASK00000001) == 0x1);
}
else
{
// Right Shift 0 < cnt <= 32
char cnt = (~DSP_ALU_SRC2_HW & MASK003F) + 1;
if (cnt > 32)
{
printf ("\nPSHA Sz,Sy,Dz Error! shift -%2X exceed range.\n", cnt);
exit ();
}
if ((cnt > 8) && DSP_ALU_SRC1G_BIT7)
{
// MSB copy
DSP_ALU_DST = (DSP_ALU_SRC1 >> 8) | (DSP_ALU_SRC1G << (32 - 8));
DSP_ALU_DST = (long)DSP_ALU_DST >> (cnt - 8);
}
else
DSP_ALU_DST = (DSP_ALU_SRC1 >> cnt) | (DSP_ALU_SRC1G << (32 - cnt));
DSP_ALU_DSTG_LSB8 = (char)DSP_ALU_SRC1G_LSB8 >> cnt--;
carry_bit = ((DSP_ALU_SRC1 >> cnt) & MASK00000001) == 0x1;
}
overflow_bit = ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 1)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
dcf psha Sx,Sy,Dz
If DC
111110 ********** 10010011 xx yy zzzz 1 1
P arallel Sh ift A rithmetically with ConditionConditionally arithmetically shifts the contents of the Sx operand and
stores the result in the Dz operand. The amount of the shift is specified by
the Sy operand. When the shift amount is positive, it shifts left. When the
shift amount is negative, it shifts right.
The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void psha_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
DSP_ALU_SRC1G = A0G;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
DSP_ALU_SRC1G = A1G;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0 & MASK007F0000;
break;
case 0x1:
DSP_ALU_SRC2 = Y1 & MASK007F0000;
break;
case 0x2:
DSP_ALU_SRC2 = M0 & MASK007F0000;
break;
case 0x3:
DSP_ALU_SRC2 = M1 & MASK007F0000;
break;
}
if (DSP_ALU_SRC2_MSB)
DSP_ALU_SRC2G = 0xFF;
else
DSP_ALU_SRC2G = 0x0;
if ((DSP_ALU_SRC2_HW & MASK0040) == 0)
{
// Left Shift 0 <= cnt <= 32
char cnt = DSP_ALU_SRC2_HW & MASK003F;
if (cnt > 32)
{
printf ("\nPSHA Sz,Sy,Dz Error! Shift %2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST = DSP_ALU_SRC1 << cnt;
DSP_ALU_DSTG = ((DSP_ALU_SRC1G << cnt)
| (DSP_ALU_SRC1 >> (32 - cnt))) & MASK000000FF;
carry_bit = ((DSP_ALU_DSTG & MASK00000001) == 0x1);
}
else
{
// Right Shift 0 < cnt <= 32
char cnt = (~DSP_ALU_SRC2_HW & MASK003F) + 1;
if (cnt > 32)
{
printf ("\nPSHA Sz,Sy,Dz Error! shift -%2X exceed range.\n", cnt);
exit ();
}
if ((cnt > 8) && DSP_ALU_SRC1G_BIT7)
{
// MSB copy
DSP_ALU_DST = (DSP_ALU_SRC1 >> 8) | (DSP_ALU_SRC1G << (32 - 8));
DSP_ALU_DST = (long)DSP_ALU_DST >> (cnt - 8);
}
else
DSP_ALU_DST = (DSP_ALU_SRC1 >> cnt) | (DSP_ALU_SRC1G << (32 - cnt));
DSP_ALU_DSTG_LSB8 = (char)DSP_ALU_SRC1G_LSB8 >> cnt--;
carry_bit = ((DSP_ALU_SRC1 >> cnt) & MASK00000001) == 0x1;
}
overflow_bit = ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
if (DC == 0)
{
DSP_REG[ex2_dz_no] = DSP_ALU_DST;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G = A0G | MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G = A1G | MASKFFFFFF00;
}
}
}
psha #imm,Dz
If imm
111110 ********** 00000 iiiiiii zzzz Update
1 1
Arithmetically shifts the contents of the Dz operand and stores the result in
the Dz operand. The amount of the shift is specified by the immediate value.
When the shift amount is positive, it shifts left. When the shift amount is
negative, it shifts right.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void psha_imm (void)
{
unsigned short tmp_imm;
DSP_ALU_SRC1 = DSP_REG[ex2_dz_no];
switch (ex2_dz_no)
{
case 0x0:
DSP_ALU_SRC1G = A0G;
break;
case 0x1:
DSP_ALU_SRC1G = A1G;
break;
default:
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
}
tmp_imm = ((EX2_LW >> 4) & MASK0000007F); // bit[10:4]
if ((tmp_imm & MASK0040) == 0)
{
// Left Shift 0 <= cnt <= 32
char cnt = tmp_imm & MASK003F;
if (cnt > 32)
{
printf ("\nPSHA Dz,#Imm,Dz Error! #Imm=%7X exceed range.\n", tmp_imm);
exit ();
}
DSP_ALU_DST = DSP_ALU_SRC1 << cnt;
DSP_ALU_DSTG = ((DSP_ALU_SRC1G << cnt)
| (DSP_ALU_SRC1 >> (32 - cnt))) & MASK000000FF;
carry_bit = (DSP_ALU_DSTG & MASK00000001) == 0x1;
}
else
{
// Right Shift 0 < cnt <= 32
char cnt = (~tmp_imm & MASK003F) + 1;
if (cnt > 32)
{
printf ("\nPSHA Dz,#Imm,Dz Error! #Imm=%7X exceed range.\n", tmp_imm);
exit ();
}
if ((cnt > 8) && DSP_ALU_SRC1G_BIT7)
{
// MSB copy
DSP_ALU_DST = (DSP_ALU_SRC1 >> 8) | (DSP_ALU_SRC1G << (32 - 8));
DSP_ALU_DST = (long)DSP_ALU_DST >> (cnt - 8);
}
else
DSP_ALU_DST = (DSP_ALU_SRC1 >> cnt) | (DSP_ALU_SRC1G << (32 - cnt));
DSP_ALU_DSTG_LSB8 = (char)DSP_ALU_SRC1G_LSB8 >> cnt--;
carry_bit = ((DSP_ALU_SRC1 >> cnt) & MASK00000001) == 0x1;
}
overflow_bit = ! (POS_NOT_OV || NEG_NOT_OV);
#include "fixed_pt_overflow_protection.c"
#include "fixed_pt_unconditional_update.c"
#include "shift_dc_bit.c"
}
Example
pshl #7,A1
! After execution: A1=0xAA800000
pshl Sx,Sy,Dz
If Sy
111110 ********** 10000001 xx yy zzzz Update
1 1
Logically shifts the top word contents of the Sx operand, stores the result in
the top word of the Dz operand, and clears the bottom word of the Dz operand
with zeros. When Dz is a register that has guard bits, the guard bits are also
zeroed. The amount of the shift is specified by the Sy operand. When the shift
amount is positive, it shifts left. When the shift amount is negative, it
shifts right.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void pshl (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0 & MASK003F0000;
break;
case 0x1:
DSP_ALU_SRC2 = Y1 & MASK003F0000;
break;
case 0x2:
DSP_ALU_SRC2 = M0 & MASK003F0000;
break;
case 0x3:
DSP_ALU_SRC2 = M1 & MASK003F0000;
break;
}
if ((DSP_ALU_SRC2_HW & MASK0020) == 0)
{
// Left Shift 0 <= cnt <= 16
char cnt = DSP_ALU_SRC2_HW & MASK001F;
if (cnt > 16)
{
printf ("\nPSHL Sx,Sy,Dz Error! Shift %2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
}
else
{
// Right Shift 0 < cnt <= 16
char cnt = (~DSP_ALU_SRC2_HW & MASK000F) + 1;
if (cnt > 16)
{
printf ("\nPSHL Sx,Sy,Dz Error! Shift -%2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
}
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = DSP_ALU_DST_HW == 0;
overflow_bit = 0x0;
#include "shift_dc_bit.c"
}
Example
pshl X0,Y0,A0
a0
! After execution: X0=0x22222222, Y0=0x00030000,
a0
pshl X1,Y1,X1
! After execution: X1=0x33330000, Y1=0xFFFE0000
dct pshl Sx,Sy,Dz
If DC
111110 ********** 10000010 xx yy zzzz 1 1
P arallel Sh ift L ogically with ConditionConditionally logically shifts the top word contents of the Sx operand, stores
the result in the top word of the Dz operand, and clears the bottom word of the
Dz operand with zeros. When Dz is a register that has guard bits, the guard bits
are also zeroed. The amount of the shift is specified by the Sy operand. When
the shift amount is positive, it shifts left. When the shift amount is negative,
it shifts right.
The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pshl_dct
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0 & MASK003F0000;
break;
case 0x1:
DSP_ALU_SRC2 = Y1 & MASK003F0000;
break;
case 0x2:
DSP_ALU_SRC2 = M0 & MASK003F0000;
break;
case 0x3:
DSP_ALU_SRC2 = M1 & MASK003F0000;
break;
}
if ((DSP_ALU_SRC2_HW & MASK0020) == 0)
{
// Left Shift 0 <= cnt <= 16
char cnt = DSP_ALU_SRC2_HW & MASK001F;
if (cnt > 16)
{
printf ("\nPSHL Sx,Sy,Dz Error! Shift %2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
}
else
{
// Right Shift 0 < cnt <= 16
char cnt = (~DSP_ALU_SRC2_HW & MASK000F) + 1;
if (cnt > 16)
{
printf ("\nPSHL Sx,Sy,Dz Error! Shift -%2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
}
if (DC == 1)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
}
}
dcf pshl Sx,Sy,Dz
If DC
111110 ********** 10000011 xx yy zzzz 1 1
P arallel Sh ift L ogically with ConditionConditionally logically shifts the top word contents of the Sx operand, stores
the result in the top word of the Dz operand, and clears the bottom word of the
Dz operand with zeros. When Dz is a register that has guard bits, the guard bits
are also zeroed. The amount of the shift is specified by the Sy operand. When
the shift amount is positive, it shifts left. When the shift amount is negative,
it shifts right.
The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits are not updated.
Operation
void pshl_dcf (void)
{
switch (EX2_SX)
{
case 0x0:
DSP_ALU_SRC1 = X0;
break;
case 0x1:
DSP_ALU_SRC1 = X1;
break;
case 0x2:
DSP_ALU_SRC1 = A0;
break;
case 0x3:
DSP_ALU_SRC1 = A1;
break;
}
switch (EX2_SY)
{
case 0x0:
DSP_ALU_SRC2 = Y0 & MASK003F0000;
break;
case 0x1:
DSP_ALU_SRC2 = Y1 & MASK003F0000;
break;
case 0x2:
DSP_ALU_SRC2 = M0 & MASK003F0000;
break;
case 0x3:
DSP_ALU_SRC2 = M1 & MASK003F0000;
break;
}
if ((DSP_ALU_SRC2_HW & MASK0020) == 0)
{
// Left Shift 0 <= cnt <= 16
char cnt = DSP_ALU_SRC2_HW & MASK001F;
if (cnt > 16)
{
printf ("\nPSHL Sx,Sy,Dz Error! Shift %2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
}
else
{
// Right Shift 0 < cnt <= 16
char cnt = (~DSP_ALU_SRC2_HW & MASK000F) + 1;
if (cnt > 16)
{
printf ("\nPSHL Sx,Sy,Dz Error! Shift -%2X exceed range.\n", cnt);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
}
if (DC == 0)
{
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
}
}
pshl #imm,Dz
If imm
111110 ********** 00010 iiiiiii zzzz Update
1 1
Logically shifts the top word contents of the Dz operand, stores the result in
the top word of the Dz operand, and clears the bottom word of the Dz operand
with zeros. When Dz is a register that has guard bits, the guard bits
are also zeroed. The amount of the shift is specified by the immediate value.
When the shift amount is positive, it shifts left. When the shift amount is
negative, it shifts right.
The DC bit of the DSR register is updated according to the specifications for
the CS bits. The N , Z , V , and GT bits of the DSR register are also updated.
Operation
void pshl_imm (void)
{
unsigned short tmp_imm;
DSP_ALU_SRC1 = DSP_REG[ex2_dz_no];
switch (ex2_dz_no)
{
case 0x0:
DSP_ALU_SRC1G = A0G;
break;
case 0x1:
DSP_ALU_SRC1G = A1G;
break;
default:
if (DSP_ALU_SRC1_MSB)
DSP_ALU_SRC1G = 0xFF;
else
DSP_ALU_SRC1G = 0x0;
}
tmp_imm = ((EX2_LW >> 4) & MASK0000003F); // bit[9:4]
if ((tmp_imm & MASK0020) == 0)
{
// Left Shift 0 <= cnt < 16
char cnt = tmp_imm & MASK001F;
if (cnt > 16)
{
printf ("\nPSHL Dz,#Imm,Dz Error! #Imm=%6X exceed range.\n", tmp_imm);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW << cnt--;
carry_bit = ((DSP_ALU_SRC1_HW << cnt) & MASK8000) == 0x8000;
}
else
{
// Right Shift 0 < cnt <= 16
char cnt = (~tmp_imm & MASK001F) + 1;
if (cnt > 16)
{
printf ("\nPSHL Dz,#Imm,Dz Error! #Imm=%6X exceed range.\n", tmp_imm);
exit ();
}
DSP_ALU_DST_HW = DSP_ALU_SRC1_HW >> cnt--;
carry_bit = ((DSP_ALU_SRC1_HW >> cnt) & MASK0001) == 0x1;
}
DSP_REG_WD[ex2_dz_no*2] = DSP_ALU_DST_HW;
DSP_REG_WD[ex2_dz_no*2+1] = 0x0; // clear LSW
if (ex2_dz_no == 0)
A0G = 0x0; // clear Guard bits
else if (ex2_dz_no == 1)
A1G = 0x0;
negative_bit = DSP_ALU_DST_MSB;
zero_bit = DSP_ALU_DST_HW == 0;
overflow_bit = 0x0;
#include "shift_dc_bit.c"
}
Example
psha #-5,A1
! After execution: A1=0xFD55555555
DSP System Control Instructions
plds Dz,MACH
Dz
111110 ********** 111011010000 zzzz 1 1
Stores the Dz operand in the MACH register.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX, and MOVY can be designated in parallel, their execution may
take two cycles.
Operation
void plds_mach (void)
{
MACH = DSP_REG[ex2_dz_no];
}
Example
plds A0,MACH
! After execution: A0=0x123456789A, MACH=0x3456789A
plds Dz,MACL
Dz
111110 ********** 111111010000 zzzz 1 1
Stores the Dz operand in the MACL register.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX, and MOVY can be designated in parallel, their execution may
take two cycles.
Operation
void plds_macl (void)
{
MACL = DSP_REG[ex2_dz_no];
}
dct plds Dz,MACH
If DC
111110 ********** 111011100000 zzzz 1 1
P arallel L oad S ystem RegisterConditionally stores the Dz operand in the MACH register.
The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX, and MOVY can be designated in parallel, their execution may
take two cycles.
Operation
void plds_mach_dct (void)
{
if (DC == 1)
MACH = DSP_REG[ex2_dz_no];
}
dct plds Dz,MACL
If DC
111110 ********** 111111100000 zzzz 1 1
P arallel L oad S ystem RegisterConditionally stores the Dz operand in the MACL register.
The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX, and MOVY can be designated in parallel, their execution may
take two cycles.
Operation
void plds_macl_dct (void)
{
if (DC == 1)
MACL = DSP_REG[ex2_dz_no];
}
dcf plds Dz,MACH
If DC
111110 ********** 111011110000 zzzz 1 1
P arallel L oad S ystem RegisterConditionally stores the Dz operand in the MACH register.
The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX, and MOVY can be designated in parallel, their execution may
take two cycles.
Operation
void plds_mach_dcf (void)
{
if (DC == 0)
MACH = DSP_REG[ex2_dz_no];
}
dcf plds Dz,MACL
If DC
111110 ********** 111111110000 zzzz 1 1
P arallel L oad S ystem RegisterConditionally stores the Dz operand in the MACL register.
The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX, and MOVY can be designated in parallel, their execution may
take two cycles.
Operation
void plds_macl_dcf (void)
{
if (DC == 0)
MACL = DSP_REG[ex2_dz_no];
}
psts MACH,Dz
MACH
111110 ********** 110011010000 zzzz 1 1
Stores the contents of the MACH register in the Dz operand.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX and MOVY can be designated in parallel, their execution may
take 2 cycles.
Operation
void psts_mach (void)
{
DSP_REG[ex2_dz_no] = MACH;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G |= MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G |= MASKFFFFFF00;
}
}
Example
psts MACH,A0
! After execution: A0=0xFF88888888, MACH=0x88888888
psts MACL,Dz
MACL
111110 ********** 110111010000 zzzz 1 1
Stores the contents of the MACL register in the Dz operand.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX and MOVY can be designated in parallel, their execution may
take 2 cycles.
Operation
void psts_macl (void)
{
DSP_REG[ex2_dz_no] = MACL;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G |= MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G |= MASKFFFFFF00;
}
}
dct psts MACH,Dz
If DC
111110 ********** 110011100000 zzzz 1 1
P arallel St ore S ystem RegisterConditionally stores the contents of the MACH register in the Dz operand.
The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX and MOVY can be designated in parallel, their execution may
take 2 cycles.
Operation
void psts_mach_dct (void)
{
if (DC == 1)
{
DSP_REG[ex2_dz_no] = MACH;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G |= MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G |= MASKFFFFFF00;
}
}
}
dct psts MACL,Dz
If DC
111110 ********** 110111100000 zzzz 1 1
P arallel St ore S ystem RegisterConditionally stores the contents of the MACL register in the Dz operand.
The instruction is executed if the DC bit is set to 1.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX and MOVY can be designated in parallel, their execution may
take 2 cycles.
Operation
void psts_macl_dct (void)
{
if (DC == 1)
{
DSP_REG[ex2_dz_no] = MACL;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G |= MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G |= MASKFFFFFF00;
}
}
}
dcf psts MACH,Dz
If DC
111110 ********** 110011110000 zzzz 1 1
P arallel St ore S ystem RegisterConditionally stores the contents of the MACH register in the Dz operand.
The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX and MOVY can be designated in parallel, their execution may
take 2 cycles.
Operation
void psts_mach_dcf (void)
{
if (DC == 0)
{
DSP_REG[ex2_dz_no] = MACH;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G |= MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G |= MASKFFFFFF00;
}
}
}
dcf psts MACL,Dz
If DC
111110 ********** 110111110000 zzzz 1 1
P arallel St ore S ystem RegisterConditionally stores the contents of the MACL register in the Dz operand.
The instruction is executed if the DC bit is set to 0.
The DC , N , Z , V , and GT bits of the DSR register are not updated.
Note
Though PSTS, MOVX and MOVY can be designated in parallel, their execution may
take 2 cycles.
Operation
void psts_macl_dcf (void)
{
if (DC == 0)
{
DSP_REG[ex2_dz_no] = MACL;
if (ex2_dz_no == 0)
{
A0G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A0G |= MASKFFFFFF00;
}
else if (ex2_dz_no == 1)
{
A1G = DSP_ALU_DSTG & MASK000000FF;
if (DSP_ALU_DSTG_BIT7)
A1G |= MASKFFFFFF00;
}
}
}